2011 TAU Workshop Program (Tentative)

Thursday, March 31, 2011

8:20-8:45am Registration and Breakfast

8:45-8:50am Welcome

Florentin Dartu (General Chair, Synopsys Inc.)

8:50-9:40am Session I: Process Variation Characterization and Chip Disposition

Chair: Chandu Visweswariah

1. "Variation Mapping From Timing Path Delay Measurements Using Compressed Sensing", Kwangok Jeong and Andrew Kahng.  slide

2. "Optimal Design Dependent Chip Disposition", Vladimir Zolotov and Jinjun Xiong.   slide

9:40-10:30am Opening Keynote Speech

"Future of Signoff ", Andrew B. Kahng slide

10:30-11:00am Break

11:00-11:45am Keynote Speech II

"Carbon-Based Green Electronics ", Kaustav Banerjee

11:45-1:15pm Lunch

1:15-2:00pm Keynote Speech III

"Nanolithography and Design/Technology Co-optimization Beyond 22nm",  David Pan slide

2:00-2:15pm Break

2:15-3:45pm Session II: Timing and Constraint Analysis

Chair: Vladimir Zolotov

1. "Extracting Device-Parameter Variations with RO-Based Sensors", Kenichi Shinkai, Masanori Hashimoto and Takao Onoye.  slide

2. Efficient and Accurate Waveform-Based Digital Gate Modeling for Timing Analysis" , Safar Hatami, Peter Feldmann and Soroush Abbaspour. slide

3. "Comparing Constraint Behavior to Determine Equivalency", Sonia Singhal, Loa Mize, Subramanyam Sripada, Szu-Tsung Cheng and Cho Moon. slide

3:45-4:00pm Break

4:00-5:30pm Session IV: Parallel Circuit Simulation

Chair: Hidetoshi Onodera

1. "Chop-SPICE: An Efficient SPICE Simulation Technique For Buffered RC Trees",  Myung-Chul Kim, Dong-Jin Lee and Igor Markov. slide

2. "Graph-based Parallel Analysis of Large Analog Circuits Based on GPU Platforms", Jianan Lu, Zhigang Hao and Sheldon X.-D. Tan. slide

3. "Variation-Aware Hierarchical and Parallel Statistical Circuit Simulation", Jui-Hsiang Liu and Charlie Chen. slide

5:40pm Reception

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Friday, April  1st, 2011

8:30-9:00am Registration and Breakfast

9:00-10:40am Session V: Living with Process Variation

Chair:  Masanori Hashimoto

1. "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning", Shuta Kimura, Masanori Hashimoto and Takao Onoye. slide

2. "Electrical Bug Model Considerations for Post-Silicon Timing Validation", Peter Lisherness, Ming Gao and Kwang-Ting Tim Cheng.  slide

3. "Testability Driven Statistical Path Selection", Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov and Jacob Abraham. slide

10:40-11:10am Break

11:10-12:00pm Keynote Speech IV

"Design, modeling, and reliability of flexible electronics", Tim Cheng slide

12:00-1:15pm Lunch

1:15-2:35pm Session VI: Power and Thermal Noise Analysis and Design

Chair: Vladimir Zolotov

1. "Decoupling for Power Gating: Sources of Power Noise and Design Strategies", Tong Xu and Peng Li. slide

2. "Efficient Wake-Up Scheduling for Multi-Core Systems", Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Shih-Chieh Chang and Diana Marculescu.  slide

3. "Efficient Thermal Computation for Ultra Mesh Grid Temperature map", Dongkeun Oh, Charlie Chung Ping Chen and Yu Hen Hu.  slide

2:35-2:45am Break

2:45-3:45pm Session VII: 3D IC Issues

Chair:  Hidetoshi Onodera

1. "Fault-Tolerant 3D Clock Network", Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi and Shih-Chieh Chang.  slide

2. "Heterogeneous Thermal Simulation for Stack Vias in 3D IC", Dongkeun Oh, Charlie Chung Ping Chen and Yu Hen Hu.  slide

3:45-4:30pm Keynote Speech V

"Our CAD challenges aren't like your CAD challenges! ", Noel Menezes

4:35-5:20pm Session VIII: Power Grid Analysis Contest

Chair:  Zhuo Li

1. "Power grid analysis benchmark development and evaluation": Zhuo Li slide

2. "Award Ceremony" , Sani Nassif

"Winners talk" A. Gold medalist B. Silver medalist C. Bronze medalist

5:20-6:00pm Keynote Speech VI

"Power Delivery and Analysis in IBM", Howard H. Smith slide