CALL FOR PAPERS – TAU 2017 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Mar 16-17, 2017 – Bay Area, CA – http://www.tauworkshop.com It has become clear that timing analysis is NO longer a solved problem. So, what are new challenges as the industry embraces 14/10nm and below, rides the wave of ultra-low-power mobile, wearable devices and jumps on the IoT bandwagon? How to meet the insatiable demands for accuracy, performance, capacity and functionality? How are multi-core and multi-machine helping? Or is it time to move onto higher level of abstraction? What about more fundamental challenges coming from process physics, 3D, variability, voltage scaling, analog effects, mixed signal modeling and validation? The TAU series of workshops provide an informal forum for practitioners and researchers working on these and other temporal aspects of analog and digital systems to disseminate early work and engage in a free discussion of ideas. The twenty-second in the TAU series, the TAU 2017 workshop invites submissions and proposals from the traditional as well as emerging areas related to the timing properties of digital electronic systems, including but not limited to the topics listed below. Timing (including incremental timing) * System-level timing * Circuit/gate-level timing * Transistor-level timing * Timing of mixed signal circuits * New types of latches, dual-edge devices, etc. Modeling and simulation * Transistor level modeling * Analog circuit modeling * Circuit level simulation * Delay models and metrics * Reliability modeling and simulation Variability * Timing analysis under variation and uncertainty * Ultra-low voltage induced variation effects * Statistical timing analysis and optimization * Sensitivity/criticality analysis * Yield analysis and optimization Power, trade-offs and optimization * Timing issues in low-power design * Power-delay tradeoffs * Timing driven layout optimization * Timing driven synthesis, re-synthesis * Circuit optimization Signal integrity * Crosstalk modeling, analysis, avoidance and optimization * Noise and glitch analysis * Variation-aware signal integrity analysis Clocking * Complex clock trees and networks * Clocking, synchronization, and skew * Clock domains, static/dynamic logic * Novel clocking schemes Characterization * Cell (library) characterization * Variation effects and corner reductions * Latch characterization * Simulation and characterization of SRAM circuits Hierarchical timing * Macro-modeling: timing, SI, power, etc. * Hierarchical optimization and signoff * Integration/Interoperation with implementation flow Emerging technologies * Full custom design analysis * Special circuit families * Timing issues for 3D ICs and TSVs * New modeling techniques and machine learning * Timing implications of emerging technologies Others * Integrated functional-temporal analysis * Formal theories and methods * Asynchronous systems * Smart sensor placement * FPGA Design and Analysis DATES Paper submission deadline: November 18, 2016 Acceptance notification: December 23, 2016 Camera ready papers due: January 13, 2017 Contest registration starts: October 3, 2016 Early binary due: February 1, 2017 Final binary due: February 15, 2017 ORGANIZATION General chair: Qiuyang Wu (Synopsys) Technical program chair: Tom Spyrou (Intel) Past chair: Debjit Sinha (IBM) Contest chair: Song Chen (Synopsys) Timing contest: Similar to prior years, TAU is organizing a timing contest. The topic for the TAU 2017 contest is “Hierarchical macro-block timing modeling (ETM)”. Details are posted on the workshop website. Winners of the contest will be awarded plaques as well as cash prizes! SUBMISSION OF PAPERS All papers must be submitted electronically via the workshop website www.tauworkshop.com. Submissions are limited to 6 pages in the double column proceedings format. In order to allow for a blind review, submitted pdf version of the papers should not contain the authors name or any direct reference to the authors. TAU is a workshop aimed at fostering a high level of professional interaction, not a conference. Copies of papers will be provided to the attendees, but the proceedings will not be published by the ACM or the IEEE. Therefore, accepted papers can still be submitted to other conferences and journals.