Title: 
 
From Recovering Time to Timing Recovery: Some Challenges for the TAU Community
 

Summary:
   
The semiconductor ecosystem faces a design crisis: design at leading nodes faces growing barriers of cost, expertise, and risk. As a result, leading players across the fabless, EDA and foundry sectors – as well as academic researchers – are aggressively exploring big-data / machine learning based approaches that can reduce human effort and schedule requirements of IC design.  Such efforts are well-aligned with the goals of the U.S. DARPA “IDEA” program, which attacks cost and schedule barriers in IC design via “no-human-in-the-loop”, 24-hour layout automation flows – including the RTL-to-GDSII flow that is central to IC implementation. The IDEA program returns the focus of EDA tool researchers to “automation”, trading away PPA in return for autonomous, “self-driving tools”, along with schedule reductions.  Timing analysis and optimization are central to realizing the IDEA program vision – in timing recovery for PPA improvement, in recovering time for reduced design schedule, and in many other purposes. This talk will review some early efforts toward an open-source, “self-driving” RTL-to-GDS tool chain, along with challenges for the TAU community that have become apparent even in the early going.

Bio:

Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder/CTO at Blaze DFM (2004-2006).  He is the coauthor of 3 books and over 400 journal and conference papers, holds 34 issued U.S. patents, and is a fellow of ACM and IEEE.  He has served as general chair of DAC, ISQED, ISPD and other conferences. He served as international chair/co-chair of the Design technology working group, and of the System Integration focus team, for the International Technology Roadmap for Semiconductors (ITRS) from 2000-2016. His research interests include IC physical design and performance analysis, the IC design-manufacturing interface, combinatorial algorithms and optimization, and the roadmapping of systems and technology.  Currently, he serves as PI of “OpenROAD”, a project in the DARPA IDEA program that seeks to develop open-source layout generation tools for die, package and board domains.