“Where is my Typical Chip? Relating Silicon Back to the Timing Sign-Off Model”

Summary

The main objective of this presentation is to provide a better appreciation of real world variations in IC manufacturing and relate them back to the arguably idealistic design models that designers have available when they design their chips. 

Designing complex, state-of-the-art SOCs is an expensive endeavor. Chip designers use complex transistor models and analysis tools to implement mixed analog and digital circuits to provide the data processing and networking needs of the future. Understanding the quality and potential shortcomings of the modeling infrastructure is critical to succeed in this high-stakes competition.

In this presentation we will discuss how the accurate classification of the dynamic performance of individual chips is critical for fab-less semiconductor companies to prepare their designs for volume production. Extensive Device Validation Testing (DVT) can only be done on a limited number of chips. This testing ensures that volume production of a design will provide good yield when manufacturing is ramped up. Therefore, DVT candidate chips must be carefully selected to represent the corners of the design and manufacturing window.

We will present a parameterized dynamic performance model for ring oscillators as a classification gauge of individual ICs. This model is then used to classify initial split lot material and first volume production wafers. In the presented example we will see that the modeling assumptions during the design can be very different from manufactured early silicon. Leveraging the availability of several performance monitors per chip we will present data estimates for the spatial performance gradients on individual dies.

The variability of chip interconnect is a growing concern in nm CMOS processes. As wire resistance increases the modeling methodology has not kept up with the challenge that it poses. We will share data from capacitance ratio measurements on a recent product that highlight substantial layer to layer interconnect variation.

Last, but not least, we will share measurement data for the effective on-chip supply voltages and its variability. which is critical in understanding the dynamic capabilities of our products.

Finally, considering the gap between models and manufactured chips raises the question if the stake holders (Foundry, EDA, Fabless Semiconductor Companies) would be able to reduce significant product development risk if they could agree and cooperate on standardized dynamic test structures, readout schemes, and analysis methodologies. There could be opportunities for the Tau community in the future by addressing the highlighted concerns.


Bio

Christian Lütkemeyer is a Senior Technical Director at Inphi Corporation through the acquisition of ClariPhy Inc. in December 2016. He joined ClariPhy in February 2016 after more than 16 years in the Office of the CTO at Broadcom Corporation where he was the leader of the Timing Sign-Off Center of Excellence when he left. At Inphi he is responsible for advanced timing sign-off methodology, efficient timing closure strategies, power integrity modeling, and the design, implementation, and analysis of innovative test structures to minimize margin waste and pessimism in adaptive voltage scaling systems. He is the inventor or co-inventor of 18 patents and earned his Dr.-Ing. Degree from Aachen University of Technology in Germany.