Title:  

Beyond CMOS – A Look at Two Promising Post CMOS Technologies: Superconducting Electronics  & Spintronics


Abstract:

For CMOS technology, currently at 7nm and pushing 5nm and 4nm, Moore’s law was a roadmap based on Dennard scaling. Achieving the roadmap from 3um to 3nm encountered plenty of obstacles and challenges but was possible mainly due to the locality of circuit effects technologists needed to deal with (capacitance and resistance). Inductive effects, while present in CMOS technology were well contained and much less significant at the frequencies CMOS operated within. Chips with tens of billions of transistors are no longer a far-fetched prospect. However, making full use of such a transistor count is highly limited by power considerations leading to architectures based on dark silicon and dim silicon.

Two energy efficient technology candidates are strongly emerging as major candidates for beyond CMOS: Superconducting Electronics (SCE) and Spintronics. And while neither superconducting electronics nor spintronics are totally new, the manner they are being considered and the recent developments in both areas makes them strong candidates for beyond CMOS VLSI. This talk will address both technologies at a high level in terms of their state of technological development and their suitability for VLSI circuits.

In this talk I will address major features and developments in spintronics that made spintronics a solid candidate for embedded memory caches, for logic devices and for ultra-compact and efficient hard disk replacement. I will be addressing STT-MRAMs, SOT-MRAMs, and Racetrack storage devices. I will briefly mention the suitability of spintronics quantum dots for quantum computing

EDA tools supporting a complete flow for CMOS VLSI integration and huge SOCs encompassing over 20 Billion transistors is a reality that is taken for granted today. The design automation for large-scale and very large-scale integration (VLSI) of SCE chips, with complexities in the one million gates, 100 million Josephson Junctions (JJ) range, is lacking and cannot be successfully fulfilled without design automation tools, standard-cells libraries, and design flows and methodologies akin to those developed for CMOS.

For superconducting electronics I will discuss a comprehensive flow aimed at enabling the VLSI realization of SCE circuits. I will address what have we learned from the CMOS experience, what can be adopted from that experience to expedite arriving at VLSI for SCE, and where do the SCE vs. CMOS similarities stop. I will address issues unique in their nature to SCE circuits such as serial power delivery and current recycling.

Bio:

Jamil is a Synopsys Fellow in the Solutions Group at Synopsys working on advanced nodes technology development and IP architectures. He is the Co-PI of the IARPA sponsored Synopsys SuperTools for Enablement of Superconducting Electronics.  Before that he was Group Director of R&D of the Implementation Group of Synopsys overseeing projects in 3-D IC and SIP design. He has been with Synopsys since 1998 where he originally managed the Memory Compiler and IO design groups before joining the Advanced Technology Group (ATG) where he worked on DFM / DFY, 3-T SRAM technology, corrugated substrate technology (for FinFET manufacturing), low power design, and Structured ASICs research.   Jamil holds over 30 patents in the areas of circuits, nano-wire devices, device reliability 3D-IC, and design architecture. He has authored over 20 papers and articles, and co-authored the book Design for Manufacturability and Yield for Nano-scale CMOS published by Springer in 2007.