siddharth_sawant.thumb.jpg

Title

Aging Timing Signoff Solutions for Automotive and IoT Applications

Speaker

Siddharth Sawant

Abstract

IC designs today require high reliability in addition to power and performance needs to enable the IoT (Internet of Things) and the automotive market. With designs reaching sub-threshold voltages, effects like aging and process variation have a big impact on operation and design. Aging effects have a huge impact on automotive and IoT products with long product life and exposure to harsh temperatures. Timing closure is a challenge due to aging effects, which cause a slowdown in the device performance. Aging as a process is fairly complex. Aging timing sign-off today is a topic that still needs to be explored and well understood. Designers today mainly rely on derate and margin-based solutions to account for aging. Conventional timing closure guard-banding for aging thus results in conservative margins and pessimistic PPA. This presentation outlines a methodology that incorporates aging reliability models along with library characterization tools to enable aging aware timing closure. We further compare and contrast QoR (Quality of Results) between conventional derate-based aging timing closure and aged libraries.

Biography

Siddharth has a Masters degree in Electrical Engineering from ASU. He is currently Member of Technical Staff within the Design Enablement group at GlobalFoundries. He leads device-margins and aging methodology solutions for customers. His other responsibilities also include characterization and variation analysis, along with customer enablement. In the past, Siddharth has worked for companies like Microchip Technology for its High-Performance Manufacturing Design group and Intel Corporation on their GPU products.