"The Evolution, Pitfalls, and Cargo Cult Engineering of Advanced Digital Timing Sign-off"

Summary

In this talk, the speaker wants to highlight how the margin innovation development in timing sign-off over the last 15 years has created significant risks of unmodeled effects for gates and interconnect. 
The talk covers the topics of

- vanishing fixed margins

- no comprehensive Multi-Input Switching modeling

- no adequate margins for layer-to-layer interconnect variation

- power integrity modeling with current source models that clobber the damping of switching CMOS circuits

- very short time (just a few clock cycles) of vector data for power integrity simulations

- Power integrity artifacts due to lumped VSS loads in demand current models for gates

- significant gaps between idealistic models for transistors and interconnect, and real silicon

 

Bio:

Christian Lütkemeyer is a Senior Technical Director at Inphi Corporation through the acquisition of ClariPhy Inc. in December 2016. He joined ClariPhy in February 2016 after more than 16 years in the Office of the CTO at Broadcom Corporation where he was the leader of the Timing Sign-Off Center of Excellence when he left. At Inphi he is responsible for advanced timing sign-off methodology, efficient timing closure strategies, power integrity modeling, and the design, implementation, and analysis of innovative test structures to minimize margin waste and pessimism in adaptive voltage scaling systems. He is the inventor or co-inventor of 18 patents and earned his Dr.-Ing. Degree from Aachen University of Technology in Germany.