ASTA for Cyclic and Asynchronous Circuits


Christos Sotiriou


STA is the cornerstone of timing in EDA. In STA, NLDM, CCS/ECSM and LVF models have been used effectively to sign-off ICs fabricated at the most advanced process nodes. However, circuits with cycles are not yet supported. This issue has for many years been a major hurdle, preventing the use of asynchronous and, in general, cyclic circuits in EDA. In this talk, we will present requirements, achievements, and open-issues in STA methodologies for cyclic circuits. We will show that it is indeed possible to time them and to compute their critical cycles. We will also review STA for a set of practical cyclic circuits including: (1) asynchronous control circuits, (2) bundled-data circuits, where the asynchronous latch control is connected to the ordinary latch-based data path, and (3) mixed cyclic-combinational circuits, where a cyclic circuit must be timed to compute setup and hold times in the non-cyclic portion.


Christos P. Sotiriou is Associate Professor in the Department of Computer Science and Electrical Engineering of the University of Thessaly. He received his Ph.D. in computer science from the University of Edinburgh in 2001. He is author of over 31 journal and conference papers and holds 7 patents. He has served as Chair of the International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) as well as other conferences and symposia. He specializes in digital circuit design, CAD tools and algorithms, and asynchronous circuit design.