Keynotes and invited talks

ASTA for Cyclic and Asynchronous Circuits

Christos Sotiriou

STA is the cornerstone of timing in EDA. In STA, NLDM, CCS/ECSM and LVF models have been used effectively to sign-off ICs fabricated at the most advanced process nodes. However, circuits with cycles are not yet supported. This issue has for many years been a major hurdle, preventing the use of asynchronous and, in general, cyclic circuits in EDA. In this talk, we will present requirements, achievements, and open-issues in STA methodologies for cyclic circuits. We will show that it is indeed possible to time them and to compute their critical cycles. We will also review STA for a set of practical cyclic circuits including: (1) asynchronous control circuits, (2) bundled-data circuits, where the asynchronous latch control is connected to the ordinary latch-based data path, and (3) mixed cyclic-combinational circuits, where a cyclic circuit must be timed to compute setup and hold times in the non-cyclic portion.

Christos P. Sotiriou is Associate Professor in the Department of Computer Science and Electrical Engineering of the University of Thessaly. He received his Ph.D. in computer science from the University of Edinburgh in 2001. He is author of over 31 journal and conference papers and holds 7 patents. He has served as Chair of the International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) as well as other conferences and symposia. He specializes in digital circuit design, CAD tools and algorithms, and asynchronous circuit design.

A Timing Methodology for Metal Variation

Chul Rim (Samsung)

While the EDA industry has been introducing advanced technologies such as LVF and parametric OCV method to consider FEOL variation, BEOL variation has been relatively neglected so far. However, BEOL variation is also a major contributor for chip variation. In 2018, Samsung introduced POCV-like method as a result of EDA collaboration to consider via resistance in a statistical manne. Metal variation is still a challenging topic. In this presentation, we show the main contributor of metal variation and how it can cause chip failure. Then we introduce a recent collaboration with EDA and its hurdles. In addition, an in-house approach is introduced.

Process related challenges in timing signoff and directions to solve them

YenPin "Kevin" Chen (TSMC)

YenPin Chen received his M.A degree in computer science from the National Taiwan University in 2006. Due to his interest in design for manufacturing, he joined TSMC and has since devoted himself to digital design flows on advanced process nodes. He is now a manager of design methodology in the kit development division, in charge of the STA signoff flow.

Statistical Analysis and Optimization Methodology for VLSI Circuits

Kelvin Le

Statistical analysis and optimization methodology, specifically statistical static timing analysis, was a hot topic and drew a lot of attention during 2003 and 2007. Many research papers were published and multiple solutions were developed from various EDA vendors, including several startup companies. However, none of these solutions were widely adopted in the market due to their intrinsic complication, difficulty in adoptions, and lack of support from the entire ecosystem. Methods such as AOCV and POCV were adopted as low cost alternatives to address various needs of variability modeling.

In recent years, there are renewed interests in statistical methodology. On one hand, the pursuit for low power design for mobile/IoT drives the circuit to operate at near threshold, which leads to exponential increasing in cell timing variability. On the other hand, continued downward scaling of transistors leads to increased impact of wire/via variability to timing, especially for high performance operations. This talk reviews various technologies developed for statistical static timing analysis, including statistical cell characterization, statistical parasitic extraction, parametric delay calculation and timing propagation, full-chip sensitivity analysis and variation-driven ECO. Given the renewed interests in statistical analysis, we believe these technologies will be useful to serve the needs of modern VLSI circuit design

Kelvin Le is a software engineer at Google. He has been in Google since Nov 2019. Before that, he worked at Synopsys since 2011, where he was one of the key developers for PrimeTime and PrimeYield. Before joining Synopsys, he worked at Extreme-DA since 2004 as one of the founding members. Extreme-DA was acquired by Synopsys in 2011. Kelvin Le received his Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University in 2006, andM.S. and B.S. degrees in Electrical Engineering from Shanghai Jiaotong University, in 2001 and 1999, respectively.

Kelvin Le's research interests include electronic design automation, machine learning, and distributed systems. He is the inventor of Parametric On-chip Variation (POCV), and one of the key contributors to Liberty Variation Format (LVF). Kelvin Le has 15+ publications and holds 10+ US patents. He is also one of the authors of the book Statistical Performance Modeling and Optimization.

Simultaneous Multi Voltage Analysis with Dynamic Voltage Frequency Scaling

Paul Berevoescu (Synopsys)

Low power has become a critical design goal for multiple applications, from ear pods and smart watches to data centers and AI applications. Low power design methodologies are now ubiquitous, with increasingly complex signoff requirements for verification across an extensive analysis space spanning multiple voltages and frequencies. Substantial time and compute resources are needed for a comprehensive coverage of this analysis space, with potential negative impact on design closure TAT. This talk reviews some of the solutions currently used to perform Static Timing Analysis of designs at multiple voltages and frequencies and introduces Simultaneous Multi Voltage Analysis with Dynamic Voltage Frequency Scaling [SMVA with DVFS], a new method reducing the exponential complexity of the current solutions to quasi linear in the number of targeted voltage levels.

Paul Berevoescu is Principal Engineer at Synopsys, driving the PrimeTime Multi Voltage Analysis solution. Prior to Synopsys, Paul held various technical positions at Intel, Cadence, AmmoCore and CLK Design Automation, focusing on Static Timing Analysis, Clock Tree Synthesis, Optimization and Chip Design. Paul received his degree in Electrical Engineering from the Technion Institute of Technology in Israel.

Robust Rare Circuit Failure Detection using Data-Efficient Machine Learning

Peng Li (University of California Santa Barbara)

Anomaly detection has become an increasingly important research problem and challenge with applications in many science and engineering domains. Advances in anomaly detection can broadly impact a broad range of use cases including verification of mission/safety-critical systems, robust manufacturing, predictive maintenance, and fraud detection.

This talk will present machine learning techniques targeting detection of rare circuit failures using severely limited amounts of training data for reasons such as high cost in data collection and/or unavailability of labeled data. As such, the key challenge to be tackled is to enable anomaly detection with desired data efficiency and robustness in high-dimensional input (feature) spaces where complex interactions of such features lead to rareness of failures.

First, we will present a data-efficient Bayesian optimization (BO) approach. At the heart of the proposed BO process is a delicate balancing between two competing needs: exploitation of the current statistical model for quick identification of highly likely failures and exploration of undiscovered feature space so as to detect hard-to-find failures over wide ranges of feature values. While one of the key benefits of BO is its generality as a black-box solution, existing BO techniques do not scale well with the dimensionality of the feature space. Dimension reduction, a key enabler for scaling learning in a high-dimensional feature space, will be introduced under the framework of Bayesian optimization. Second, a self-labeling approach for unsupervised learning and detection of anomalies where no labeled training data is assumed will be presented. Finally, general issues of robust machine learning in terms of model uncertainty and resilience with respect to various local and global attacks will be discussed. The proposed amorally detection techniques will be demonstrated under the context of analog/mixed-signal IC design verification and post-manufacturing test for safety-critical automotive applications with stringent failure rate requirements, e.g. less than one detective parts per million (DPPM).

Peng Li received the Ph. D. degree from Carnegie Mellon University in 2003. He was on the faculty of Texas A&M University from August 2004 to June 2019. Since July 2019, he has been with the University of California at Santa Barbara as a professor of Electrical and Computer Engineering.

His research interests are in integrated circuits and systems, electronic design automation, brain-inspired computing, and robust machine learning. Li’s work has been recognized by an ICCAD Ten Year Retrospective Most Influential Paper Award, four IEEE/ACM Design Automation Conference (DAC) Best Paper Awards, an Honorary Mention Best Paper Award from ISCAS, an IEEE/ACM William J. McCalla ICCAD Best Paper Award, two SRC Inventor Recognition Awards, two MARCO Inventor Recognition Awards, and an NSF CAREER Award. He was honored by the ECE Outstanding Professor Award, and was named the TEES Fellow, William O. and Montine P. Head Faculty Fellow, and Eugene Webb Fellow by the College of Engineering at Texas A&M University. He was the Vice President for Technical Activities of the IEEE Council on Electronic Design Automation from Jan. 2016 to Dec. 2017. He is a Fellow of the IEEE and has consulted for Intel and two Silicon Valley startup companies.

Future of Simulation-Based Product Innovation in the Digital World

Prithviraj "Prith" Banerjee (Ansys)

Digital transformation refers to the use of digital technologies such as cloud, IOT, AI/ML, to transform the way business is executed. Digital transformation is impacting every industry - automotive, agriculture, logistics, healthcare and manufacturing. In the past, engineered products were designed with mechanical and electrical CAD tools, simulated and validated for correctness with CAE tools, prototypes were fabricated and tested, and products were then manufactured at scale in factories. This process required long product cycles often requiring years to build a new product. Today, one can use unlimited computing and storage available from the cloud to do generative design to explore 10,000 design choices in near real-time, verify these products accurately through simulation (eliminating the need to build physical prototypes) and manufacture the products using additive manufacturing and factory automation (Industry 4.0). In this talk I will discuss how the ANSYS Pervasive Simulation Platform allows hardware and software developers to work together in all phases of a product development lifecycle including Ideation, Design Manufacturing, and Operations. Simulation tools are increasingly being used in the ideation phase by designers to get real-time simulation of the parts as soon as they are being conceptualized. This has resulted in shorter, agile product cycles even for hardware products allowing innovative products to be designed and produced in months and days. Companies are increasingly using model-based systems engineering concepts to take high level requirements of products, and manage the complexity of product design using concepts of Digital Threads, Digital Twins, and Digital Continuity. We will touch upon some future directions of simulation-based product innovation around AI/Machine Learning, Multi-physics Platforms, Hyperscale Simulation, and the convergence of the Digital and Physical worlds using IOT and Augmented Reality/Virtual Reality.

Prith Banerjee is the Chief Technology Officer of ANSYS where he is responsible for leading the evolution of ANSYS' Technology strategy and champion the company’s next phase of innovation and growth. He also serves on the Board of Directors of Cray, Inc. and Cubic Corporation. Previously he used to be Senior Client Partner at Korn Ferry where he was responsible for IOT and Digital Transformation in the Global Industrial Practice. Formerly, he was Executive Vice President, Chief Technology Officer of Schneider Electric. Previously, he was Managing Director of Global Technology Research and Development at Accenture. Formerly, he was Chief Technology Officer and Executive Vice President of ABB. Earlier, he was Senior Vice President of Research at HP and Director of HP Labs. Formerly, he was Dean of the College of Engineering at the University of Illinois at Chicago. Formerly, he was the Walter P. Murphy Professor and Chairman of Electrical and Computer Engineering at Northwestern University. Prior to that, he was Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. In 2000, he founded AccelChip, a developer of products for electronic design automation, which was acquired by Xilinx Inc. in 2006. During 2005-2011, he was Founder, Chairman and Chief Scientist of BINACHIP Inc., a developer of products in electronic design automation. He was listed in the FastCompany list of 100 top business leaders in 2009. He is a Fellow of the AAAS, ACM and IEEE, and a recipient of the 1996 ASEE Terman Award and the 1987 NSF Presidential Young Investigator Award. He received a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.

Efficient Parasitic Interconnect Insertion for Timing Analysis

Ronald A. Rohrer (Southern Methodist University)

Adjoint sensitivity analysis is employed efficiently to obtain the signal droop –deviation from ideal response—caused by parasitic interconnect among gates. A linear analog inertial delayed Elmore Delay digital gate macromodel used in conjunction with the above renders efficient overall timing analysis.

One of the preeminent researchers in electronic design automation, Ron Rohrer’s contributions to improving integrated circuit (IC) production span over 50 years. Rohrer realized early on that circuit simulation was crucial to all aspects of IC design, and introduced a sequence of projects in courses at UC Berkeley that evolved into SPICE, now the industry standard for IC simulation. Decades later at Carnegie Mellon University, he introduced the Asymptotic Waveform Evaluation (AWE) algorithm, which enabled efficient timing simulation of ICs containing extremely large numbers of parasitic elements.

He is a legendary inventor, author & co-author of 5 patents, 5 textbooks and more than 100 technical papers. He was founding editor of the Institute of Electrical and Electronics Engineers (IEEE) Transactions on Computer-Aided Design of Integrated Circuits and Systems from 1981-1984 and President of the Circuits and Systems Society of the IEEE in 1987. Rohrer was made Fellow, IEEE in 1980, and inducted into the National Academy of Engineering in 1989. He has served on numerous AIEE, IEEE, NAE and US Government committees.

His contributions to the field have also been acknowledged by major awards, including the IEEE Kirchhoff Award in 2012, the IEEE CAS Belevitch Award in 2009, the EDAC Phil Kaufman Award in 2002, the NEC Corp. C&C Prize in 1996, the IEEE Education Medal in 1993, and the SRC Technical Excellence Award in 1991, the IEEE CAS Van Valkenburg Award in 1990, the SRC Inventor Recognition Award in 1990, and the ASEE Terman Award in 1978. Rohrer was granted the Senior Humboldt Fellowship, RWTH, Aachen from1972-1973, and four other acknowledgements for prize papers between 1967 and1991.

In addition to his academic career, he has been involved in over a dozen start-ups and has held executive positions in publicly traded companies. Rohrer is currently the Cecil & Ida Green Professor of Electrical and Computer Engineering in the Lyle School of Engineering at Southern Methodist University’s (SMU).

Aging Timing Signoff Solutions for Automotive and IoT Applications

Siddharth Sawant

IC designs today require high reliability in addition to power and performance needs to enable the IoT (Internet of Things) and the automotive market. With designs reaching sub-threshold voltages, effects like aging and process variation have a big impact on operation and design. Aging effects have a huge impact on automotive and IoT products with long product life and exposure to harsh temperatures. Timing closure is a challenge due to aging effects, which cause a slowdown in the device performance. Aging as a process is fairly complex. Aging timing sign-off today is a topic that still needs to be explored and well understood. Designers today mainly rely on derate and margin-based solutions to account for aging. Conventional timing closure guard-banding for aging thus results in conservative margins and pessimistic PPA. This presentation outlines a methodology that incorporates aging reliability models along with library characterization tools to enable aging aware timing closure. We further compare and contrast QoR (Quality of Results) between conventional derate-based aging timing closure and aged libraries.

Siddharth is a Senior Member of Technical Staff within the Design Enablement group at GlobalFoundries. He leads device-margins and aging methodology solutions for customers. His expertise includes library characterization, front-end implementation, timing sign-off, and variation analysis, along with customer enablement. In the past, Siddharth has worked for companies like Microchip Technology for its High-Performance Manufacturing Design group and Intel Corporation on their GPU products. He has authored and presented multiple papers on aging and variation techniques at leading industry conferences. He has a M.S. degree in Electrical Engineering from Arizona State University.

On premise and AWS Cloud enablement of Xilinx design capture and closure flows using Ansys Path FX

Simon Burke and Nitin Navale

As a major FGPA manufacturer, Xilinx Inc. has many challenges when using standard EDA tools in unique and non standard ways to deliver our products to our customers. Some of those challenges relate to scale out execution of compute intensive flows and cloud enablement of EDA tools and ecosystem is one option Xilinx is pursuing to address some of those challenges. This presentation will describe the use of Ansys’s Path FX tool both on premise and on Amazon AWS cloud environment to address some of those scale out limitations, specifically related to timing capture of delay information for our priority PnR tools.

The OpenROAD project : Goals, demo, and code organization

Tom Spyrou (OpenROAD)

Tom will give an overview of the OpenROAD open source EDA project. He will discuss the goals of the project and how it fits into a healthy research ecosystem. Tom will also discuss the software architecture, show some code examples, and then conclude with a short demo.

Tom Spyrou is the chief architect and technical program manager for the OpenROAD system. Tom is a well-known EDA system architect. He was most recently a Senior Principal Engineer in Intel’s Programmable Solutions business unit working on the Quartus FPGA compiler. Tom has worked for over 30 years as an EDA Technologist and has gained extensive experience in areas including Static Timing Analysis, Logic Synthesis, Power Grid Analysis, Database Technology and Floor-planning. He has led the development of leading edge commercial engines and products such as PrimeTime, Voltage Storm, First Encounter, and the Open Access Database. Tom has been driving EDA algorithms to utilize parallel programming approaches with both multi-process and multi-threaded techniques. He has a BS from Carnegie Mellon University in ECE and an MS from Santa Clara University.