Applying static timing analysis techniques to novel superconducting logic families

Abstract

Superconducting logic families based on Josephson junctions offer the potential for very low power, high speed operation of digital logic. The superconducting properties that enable this potential also create challenges for traditional static timing. This presentation will begin with a brief overview of superconducting circuits, followed by an analysis of the static timing challenges, and finally a description of how we adapted our static timing approach to handle these challenges for one family of superconducting logic.

Biography

Alex Braun is a Software Architect in Cadence’s Digital Signoff Group working on advanced modeling for timing analysis of both CMOS and superconducting circuits. Previously, Alex has done extensive work with the RQL (Reciprocal Quantum Logic) family of superconducting logic including digital implementation, logic cell design, and modeling for timing and variation. Alex has a BS in Computer Engineering from the Rochester Institute of Technology.