UPSET: SET Analysis and Optimization Flow for VLSI circuits based on Static Timing Analysis and Closed-loop IN-place Optimizations

Abstract

In this talk, we will review novel EDA flows and tools for analysing and optimising digital, large scale space IPs (~1M standard-cell), susceptible to SETs or SEUs. Deviating from simulation-based and analytical methods, such as TCAD or SPICE level electrical analysis, we will present industry-proven Static, Timing Analysis (STA) EDA methodologies. EDA, STA-based SET, SEU analysis is capable of performing vectorless, probabilistic analysis, computing the total number of Accumulated SETs (ASETs) at circuit endpoints and identifying SET/SEU critical gates through various criticality metrics. The probabilistic nature of the analysis is useful for pruning low probability SET/SEU errors, and focusing on the most critical circuit sections. STA-based analysis is not only ~25K times faster than electrical simulation, but takes into account the complete circuit picture, i.e. the physical circuit representation, separating cell delays, slews and layout wire RC delays, slews. It may be used during any EDA flow IC implementation steps, post-synthesis to pre-GDSII and does not require specific SET based characterisation, as it is based on standard technology timing library data, Liberty, LEF files and captables. Its analysis speed allows for it to be used in novel EDA closed loop SET/SEU In-Place Optimisation (IPO) algorithms. A rich set of cell and layout changes may be tested, fully-automatically by IPO and used, with user guidance if needed, including spacing of specific individual cells or groups to avoid SEMTs, moving invidual cells thus controlling wire RC delays/slews, cell upsizing/downsizing, buffer insertion, insertion of guard gates, and even incremental synthesis. The IPO algorithm thus evaluates different fault tolerant techniques to fix individual high probability critical SET issues, and improve endpoint ASETs or lower their probability. This novel EDA flows and tools allow for a new tradeoff to be explored, i.e. between circuit performance and SET/SEU reliability. Performance may be reduced, with the circuit slowing down, in terms of its clock period, but its SET/SEU robustness will be increased!

Biography

Christos P. Sotiriou is Associate Professor in the Department of Computer Science and Electrical Engineering of the University of Thessaly. He received his Ph.D. in computer science from the University of Edinburgh in 2001. He is author of over 31 journal and conference papers and holds 7 patents. He has served as Chair of the International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) as well as other conferences and symposia. He specializes in digital circuit design, CAD tools and algorithms, and asynchronous circuit design.