Transistor Model Development for Cryo-IC Design Environment

Abstract

In quantum computers that operate at cryogenic temperatures, the number of wires between the dilution refrigerator and room temperature is the most significant factor that hinders their scalability. To address the issue, an attempt to suppress the increase in the number of wires by operating CMOS control circuits installed at room temperature at cryogenic temperatures (Cryo-CMOS) is considered promising. On the other hand, a transistor model that can accurately simulate the CMOS transistor characteristics at cryogenic temperatures is essential for efficiently designing large-scale integrated circuits. In this presentation, we will review the following modeling methods for Cryo-CMOS transistors: 1) BSIM, which is an industry standard model; 2) the machine-learning-based modeling method, which has recently attracted attention; and 3) the modeling method based on cryogenic device physics. We also discuss the pros and cons of each method and provide a future direction.

Biography

Michihiro Shintani received a Ph.D. degree from Kyoto University, Kyoto, Japan, in 2014. He is with the Graduate School of Science and Technology, Kyoto Institute of Technology, Kyoto, Japan, where he is currently an Associate Professor.