2004 ACM/IEEE TAU Workshop
on Timing Issues in the Specification and Synthesis of Digital Systems
www.tauworkshop.com
Sponsored by ACM/SIGDA and IEEE Circuits and
Systems Society
Additional support
from Cadence, IBM, Intel, and Magma Design Automation
FINAL
PROGRAM
MONDAY, FEBRUARY 2
8:45 9:45 am Welcome and Keynote
Host: C. Alpert/IBM
Keynote Address: Jim Kahle (IBM)
The Myth of the optimal FO4
This talk will summarize the performance parameters that guide effective
microprocessor design and review the role of frequency tuning and goals towards
achieving design closure. In practice, designing to an FO4 has been a good rule
of thumb, but as technology scales, many factors erode its effectiveness. For
example, FO4 does not capture wire delays and back-end scaling. New rules of
thumb measurements for achieving timing goals need to be established that
capture the deep sub-micron effects of todays designs.
This talk will also reflect on recent work on optimal pipeline structures and
show how technology and
power limitations will change these optimizations in the future. New
technology directions will continue to drive next-generation microprocessors.
9:45 10:10 am Break
10:10 am noon Statistical Timing Topics
Chair: D. Blaauw (Michigan)
Fast Computation of Circuit Delay Probability Distribution for Timing Graphs with Arbitrary Node Correlations
M. Orshansky (UT-Austin)
First-Order Parameterized Block-Based Statistical Timing Analysis
C. Visweswariah, K. Ravindran, K. Kalafala (IBM)
Statistical Gate Sizing to Increase Timing Yield
S. Raj, S. Vrudhula, J. Wang (U-Arizona)
The Count of Monte Carlo
L. Scheffer (Cadence)
Noon 1:30 pm Lunch
1:30 3:20 pm Topics in Timing
Chair: S. Hassoun (Tufts)
A Fast Oracle for Interconnect Delay Prediction
C. Alpert (IBM), J. Hu (Texas A&M), S. Sapatnekar (Minnesota), C-N. Sze
Synchronous Wave Pipelining for High Throughput Interconnect System
L. Zhang; Y. Hu; C.C.P. Chen (Wisconsin)
Advanced Waveform Models for the Nanometer Regime
S.R. Nassif, E. Acar (IBM)
Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals
P. Feldmann, F. Liu (IBM)
3:20 3:50 pm Break
3:50 5:20 pm Focus Group Discussions
Chair: D. Sylvester (Michigan)
Topics:
1. Statistical Static Timing Analysis and Optimization: Sizzle or Fizzle?
(Group lead: C. Visweswariah)
2. Impact of Power/ground Noise on Timing
(Group lead: S. Nassif)
3. Buffering Resource Requirements due to Scaling (Group lead: D. Kirkpatrick)
4. Most Significant Timing Contributions + TAU 2009 Predictions (Group lead: TBD)
(Including brief reports from Groups 2-4)
6:30 9:30 pm Dinner
"Fun and Games at Dave & Busters" - Taxis leave from the Renaissance hotel lobby at 6:30
TUESDAY, FEBRUARY 3
8:45 10:00 am Is Statistical Timing Useful?
Chair: F. Dartu (Intel)
Achieving Frequency in a High Performance Microprocessor: Why Statistical Timing is not on my Tools Wish List (invited)
C. Anderson (IBM)
Probabilistic and Variation-Tolerant Design: Key to Continued Moore's Law Scaling (invited)
T. Karnik (Intel)
Focus Group 1 Report: SSTA/Optimization: Sizzle or Fizzle?
10:00 10:30 am Break
10:30 am noon Advanced Delay Modeling
Chair: S. Nassif (IBM)
Modelling Flip-Flop Delay Dependencies in Timing Analysis
A.M. Jain, D. Blaauw (Michigan)
Timed Input Pattern Generation for Delay Calculation under Simultaneous Switching
S.H. Choi (Purdue), F. Dartu (Intel), K. Roy
False Coupling Exploration in Timing Analysis
K. Tseng (Cadence), M. Horowitz (Stanford)
Noon 1:30 pm Lunch
1:30 2:50 pm Cell-level Delay Models
Chair: L. Scheffer (Cadence)
Towards More Accurate Cell Modeling (invited)
G. Rao (Magma)
Cell-Level Models are Hopelessly Inadequate (invited)
K. Tseng (Cadence)
Cell-Level Models are Accurate and Essential (invited)
B. Mullen (Synopsys)
2:50 3:20 pm Break
3:20 pm 5:10 pm Interconnect-Driven Timing
Issues
Chair: V. Zolotov (Motorola)
A Robust Cell-Level Crosstalk Delay Change Analysis
I. Keller, K. Tseng, N. Verghese (Cadence)
Worst-Case RLC Noise with Timing Window Constraints
J. Chen, L. He (UCLA)
An Efficient Merging Scheme for Clock Routing with General Skew Targets
R. Chaturvedi, J. Hu (Texas A&M)
Integrity-Driven Power and Signal Network Codesign
J. Xiong, L. He (UCLA)
5:10 pm Closing Remarks
TAU Organization
General Chair: C. J. Alpert (IBM)
Program Chairs: L. Scheffer (Cadence), D. Sylvester (Michigan)
Program Committee: D. Blaauw (Michigan), L. Chen, F. Dartu (Intel), V. Kariat (Cadence), S. Hassoun (Tufts), C. Kashyap (Flex-Logic), D. Kirkpatrick (Intel), K. Kucukcakar (Synopsys), L. Pileggi (Carnegie-Mellon), V. Rao (IBM), S. S. Sapatnekar (Minnesota), M. Singh (UNC), H. Zhou (Northwestern), V. Zolotov (Motorola)