TAU 2006 Technical Program
	Monday, Feb 27
Breakfast	8:00 - 8:30		Breakfast, Registration
Session 1	8:30-8:35		Introductory Remarks	Lou Scheffer/Vinod Kariat
	8:35-9:00	1.A	Why are Timing Estimates so Uncertain? What could we do about this?	Lou Scheffer
	9:00-9:25	1.B	A PLA based Asynchronous Micropipelining Approach for Subthreshold Circuit Design	Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P Khatri
	9:25-9:50	1.C	SELF: Specification and design of synchronous elastic circuits	Jordi Cortadella, Mike Kishinevsky, Bill Grundmann
	9:50-10:15		Technology Mapping for Robust Asynchronous Threshold Networks	Cheoljoo Jeong and Steven M. Nowick
Break	10:15-10:45		Break
Session 2	10:45-11:10	2.A	Timing analysis in presence of voltage drops and temperature gradients	Benoit LASBOUYGUES, Robin WILSON, Nadine AZEMARD, Philippe MAURINE
	11:10-11:35	2.B	A Multi-port Current Source Model for Multiple Input Switching Effects in CMOS Library Cells	Chirayu Amin, Chandra Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout
	11:35-12:00	2.C	Current Source Driver Model Synthesis and Worst-case Alignment for Accurate Timing and Noise Analysis	Kaviraj Chopra, Chandramauli Kashyap, Haihua Su, David Blaauw
	12:00-12:15	2.D	Standard Cell Characterization Considering Lithography Induced Variations	Ke CAO, Jiang HU
Lunch	12:15-1:30		Lunch
Session 3	1:30 - 2:30	3.A	Panel	Organizer: Florentin Dartu
	2:30-2:45	3.B	Clock Skew Optimization for Minimizing Peak Power	Kambiz Rahimi
	2:45-3:00	3.C	A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations	Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa and Takao Onoye
	3:00-3:25	3.D	Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models	Desta Tadesse, David Sheffield, Michael Black, R. I. Bahar, Joel Grodstein
Break	3:25-3:45		Break
Session 4	3:45-4:10	4.A	A Placement Methodology for Robust Clocking	Ganesh Venkataraman, Jiang Hu
	4:10-4:35	4.B	An Efficient Retiming Algorithm Under Setup and Hold Constraints	Chuan Lin Hai Zhou
	4:35-5:00	4.C	Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow	Chuan Lin, Hai Zhou, and Aiguo Xie
	5:00-5:25	4.D	Fast Electrical Correction Using Resizing and Buffering	S. K. Karandikar, C. J. Alpert, M. C. Yildiz, P. G. Villarrubia, S. T. Quay and T. Mahmud
	5:25-5:50	4.E	Timing-Aware Decap Allocation in Power Distribution Networks	Sanjay Pant, David Blaauw
Dinner	6:00-9:00		Dinner
	Tuesday, Feb 28
Breakfast	8:00-9:00		Continental Breakfast
Session 5	9:00-9:25	5.A	Martingales : a structure for statistical timing analysis	Narendra Shenoy
	9:25-9:50	5.B	Refined Statistical Static Timing Analysis Through Learning Spatial Delay Correlations	Benjamin N Lee, Li-C. Wang, Magdy S. Abadir
	9:50-10:15	5.C	Static Timing Analysis Based on Partial and Distribution-Free Probabilistic Descriptions of Delay Uncertainty	Wei-Shen Wang, Vladik Kreinovich, and Michael Orshansky
	10:15-10:40	5.D	Criticality Computation in Parameterized Statistical Timing	Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
Break	10:40-11:00		Break
Session 6	11:00-11:25	6.A	A New Statistical Max Operation for Propagating Skewness in Statistical Timing Analysis	Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester
	11:10-11:35	6.B	Stochastic Logical Effort and Smart Monte Carlo for Timing Yield Estimation and Optimization	Alper Demir and Serdar Tasiran
	11:35-12:00	6.C	Statistical Timing Analysis with Correlated Non-Gaussian Parameters using Independent Component Analysis	Jaskirat Singh and Sachin Sapatnekar
Lunch	12:00-2:00		Lunch