Advance Program

Monday, February 23, 2009

8:20-8:45am Registration and Breakfast

8:45-8:50am Welcome

F. Liu (General Chair, IBM)

8:50-10:30am Session I: Timing Analysis: Theory and Practice

Chair: Peng Li (Texas A&M)

1. “A Hierarchical Transistor and Gate Level Statistical Timing Flow for Microprocessor Designs”
A. Bhanji, C. Visweswariah, D. Sinha, G. Ditlow, K. Kalafala, N. Venkateswaran and S. Gupta (IBM)

2. “A Gaussian Mixture Model for Propagating Distributions of Delay and Slew Together”
S. Takahashi and S. Tsukiyama (Chuo Univ., Japan)

3. “Automatic Pessimism Reduction for Multiple-Input Switching During Static Timing”
M. Govindaraj, L. Jones and S. Zhou (Synopsys)

4. “System-level Clustering and Timing Analysis for GALS-based Dataflow Architectures”
C. Shen and S. Bhattacharyya (Univ. of Maryland)

10:30-11:00am Break

11:00-11:45am Keynote Speech I

“A Sub 2W Low Power IA Processor for Mobile Internet Devices in 45nm Hi-K Metal Gate CMOS”
Gian Gerosa (Intel)

11:45-1:15pm Lunch

1:15-2:30pm Session II: Timing-Driven Physical Optimization I

Chair: Paul Morton

1. “Fast Algorithms for Optimal Timing-Driven Cell Cloning under Linear Delay Model”
Z. Li, S. Hu, D. Papa, C. Alpert, W. Shi, C. Sze and Y. Zhou (IBM, Michigan Technological Univ. and Texas A&M Univ.)

2. “Analytical Formulation of Timing Objective in Standard Cell Placement”
L. Kraginskiy and A. Ayupov (Intel, Russia)

3. “iRetILP: An Efficient Incremental Algorithm for Min-period Retiming under General Delay Model”
D. Das, J. Wang and H. Zhou (Northwestern Univ. and Illinois Inst. of Tech.)

2:30-3:00pm Break

3:00-4:15pm Session III: Parameterized Timing: Metrics and Applications

Chair: Xin Li (CMU)

1. “Statistical Ordering of Correlated Timing Quantities and its Application for Path Ranking”
J. Xiong, C. Visweswariah and V. Zolotov (IBM)

2. “Quantifying Robustness Metrics in Parameterized Static Timing Analysis”
K. Heloue, C. Kashyap and F. Najm (Univ. of Toronto and Intel)

3. “Statistical Multilayer Process Space Coverage for At-Speed Test”
J. Xiong, Y. Shi and V. Zolotov and C. Visweswariah (IBM and UCLA)

4:15-4:45pm Break

4:45-6:00pm Session IV: Variability and Characterization

Chair: Chandramouli Kashyap (Intel)

1. “A Statistically Optimal Framework for Minimum-Cost Silicon Characterization of Nanoscale Integrated Circuits”
X. Li, R. Rutenbar and S. Blanton (Carnegie Mellon Univ.)

2. “Predictive Modeling of Layout-Dependent Stress Effect in Scaled CMOS Design”
C. Wang, W. Zhao, M. Chen, F. Liu and Y. Cao (Arizona State Univ. and IBM)

3. “Adaptive Transistor Model for Fast Circuit Simulation”
J. Ni, M. Chen, Y. Cao and X. Li (Arizona State Univ. and Carnegie Mellon Univ.)

6:30pm Reception

Tuesday, February 24, 2009

8:30-9:00am Registration and Breakfast

9:00-10:40am Session V: Driver and Waveform Modeling

Chair: Igor Keller (Cadence)

1. “A Gate Delay Model over Wide-Range of Process and Environmental Variability”
K. Shinkai and M. Hashimoto (Osaka Univ., Japan)

2. “A Moment-Based Effective Characterization Waveform for Static Timing Analysis”
D. Ling, S. Abbaspour, P. Feldmann and C. Visweswariah (IBM)

3. “Worst-Case Aggressor-Victim Alignment with Current-Source Driver Models”
R. Gandikota, D. Blaauw, L. Ding and P. Tehrani (Univ. of Michigan and Synopsys)

4. “Solver for Current Source Type Drivers and Interconnect with Linear or Nonlinear Loads”
A. Ruehli and J. Hayes (IBM)

10:40-11:10am Break

11:10-12:00pm Invited Talk

“Statistical Timing: Where's the Tofu?”
N. C. Buck, E. A. Foreman, P. A. Habitz, J. G. Hemmett, S. G. Shuma, N. Venkateswaran, C. Visweswariah and X. Wang (IBM)
Speaker: C. Visweswariah

12:00-1:30pm Lunch

1:30-2:20pm Keynote Speech II

“Microelectronics- the Beginning of the End, or the End of the Beginning?”
S. Banerjee, F. Register, E. Tutuc, A. Macdonald, D. Reddy and D. Basu (UT-Austin)
Speaker: S. Banerjee

2:20-2:40pm Break

2:40-3:30pm Session VI: Timing-Driven Physical Optimization II

Chair: Jinjun Xiong (IBM)

1. “A Fully Polynomial Time Approximation Scheme for Minimum Cost Timing Driven Buffering”
S. Hu, Z. Li and C. Alpert (Michigan Technological Univ. and IBM)

2. “An Efficient Approach to Simultaneous Gate Sizing and Vt Assignment”
Y. Liu and J. Hu (Texas A&M Univ.)