Workshop Program

Thursday, March 18, 2010

8:20-8:45am Registration and Breakfast

8:45-8:50am Welcome

Peng Li (General Chair, Texas A&M University)

8:50-10:30am Session I: Design and Optimization

Chair: Ken Stevens (Univ. of Utah)

1. Scalable Asynchronous Hardware Protocol Verification for Compositions with Relative Timing
Krishnaji Desai and Kenneth Stevens (Univ. of Utah)

2.  Surrogating Circuit Design Solutions with Robustness Metrics
Jin Sun and Janet Wang (Univ. of Arizona)

3.  Toward Efficient Large-Scale Performance Modeling of Integrated Circuits via Multi-Mode/Multi-Corner Sparse Regression
Wangyang Zhang, Tsung-Hao Chen, Ming-Yuan Ting and Xin Li (Carnegie Mellon Univ. and Mentor Graphics)

4. Design and Timing Optimization of a 3D Stacked Microprocessor
Young-Joon Lee, Chang Liu, Mohit Pathak, Moongon Jung and Sung Kyu Lim (Georgia Inst. of Tech.) 

10:30-11:00am Break

11:00-11:45am Keynote Speech I

STA Challenges: Past, Present and the Future
Ahsan Bootehsaz (Synopsys, Inc.)

11:45-1:15pm Lunch

1:15-2:00pm Invited Talk

IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Validation of Robust Systems
Subhasish Mitra (Stanford Univ.)

2:00-2:15pm Break

2:15-3:55pm Session II: Timing Analysis

Chair: Peivand Tehrani (Synopsys, Inc.)

1. Automated Path Specification for Static Timing Analysis of Relative Timing Designs
Eric Quist and Peter Beerel (University of Southern California)

2. Bounded Transactional Timing Analysis
David Papa, Michael Moffitt, Charles Alpert and Igor Markov (University of Michigan and IBM) 

3. Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation
Takashi Enami, Shinyu Ninomiya, Ken-ichi Shinkai, Shinya Abe and Masanori Hashimoto (Osaka University)

4. Aging model for timing analysis at register-transfer-level
Dominik Lorenz, Ulf Schlichtmann, Georg Georgakos, Martin Barke and Daniel Müller-Gritschneder (Technische Universität München and Infineon)

3:55-4:30pm Break

4:30-5:45pm Session IV: Circuit Optimization

Chair: Charlie Chen (National Taiwan University)

 1. The Multi-Core Parallel Stochastic Optimization For Variation-Aware Layer Assignment
Xiaodao Chen and Shiyan Hu (Michigan Technological Univ.)

2. A Novel Cross Entropy Approach To On-Chip Decap Budgeting
Xueqian Zhao, Yonghe Guo, Shiyan Hu and Zhuo Feng (Michigan Technological Univ.)

3.  A Discretized Network Flow Technique for Timing-Driven Stress-Aware Chip Placement Perturbation
Chen Liao, Xiaodao Chen and Shiyan Hu (Michigan Technological Univ.)

6:30pm Reception

Friday, March 19, 2010

8:30-9:00am Registration and Breakfast

9:00-10:40am Session IV: Living with Process Variation

Chair: Xin Li (CMU)

1. Representative Path Selection for Post-Silicon Timing Prediction under Variability
Lin Xie and Azadeh Davoodi (University of Wisconsin - Madison)

2. Reducing Delay Uncertainty in Deeply Scaled Integrated Circuits Using Interdependent Timing Constraints
Emre Salman and Eby Friedman (University of Rochester) 

3. Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability
A.K.M Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi and Hidetoshi Onodera (Kyoto University)

4. Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-chip Sensors
Shinya Abe, Kenichi Shinkai, Masanori Hashimoto and Takao Onoye (Osaka University)

10:40-11:10am Break

11:10-12:00pm Keynote Speech II

Microprocessor Design in the Nanoscale Era
Speaker:  Stefan Rusu (Intel Co.)

12:00-1:15pm Lunch

1:15-2:30pm Session II: Timing for New Technologies

Chair: Igor Keller (Cadence)

1. Timing Driven Buffer Insertion For Carbon Nanotube Interconnects
 Jia Wang and Shiyan Hu (Michigan Technological Univ.)

2. A Transceiver Insertion Framework for On-Chip Optical Integration
Xiaodao Chen and Shiyan Hu (Michigan Technological Univ.)

3. Performance Modeling of a Hierarchical Multi-Algorithm Parallel Circuit Simulator
 Xiaoji Ye and Peng Li (Texas A&M Univ.)

2:30-2:50pm Break

2:50-3:40pm Session VI: Yield considerations

Chair: Chirayu Amin (Intel Co.)

1. Transistor Sizing of Custom High-Performance Digital Circuits With Parametric Yield Considerations
Daniel Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov and Yifang Liu (IBM and Texas A&M Univ.)

2. Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis
Kentaro Katayama, Takanori Date, Shiho Hagiwara, Hiroyuki Ochi and Takashi Sato (Kyoto Univ. and Tokyo Inst. Of Tech.)