Selected Tau 2002 Presentations

• Explicit Computation of Performance as a function of Process Variation , L. Scheffer (Cadence)
• A Probabilistic Approach to Clock Cycle Prediction, J. Dambre (Ghent U)
• Timing Analysis Challengtes for High Speed CPU's at 90nm and Below, A. Efrati (Intel)
• Death, Taxes and Failing Chips, C. Visweswariah (IBM)
• Minimum-Power Retiming for Dual-Supply CMOS Circuits, F. Sheikh, K. Keutzer (Berkeley), A. Kuehlmann (Cadence)
• PERI: A technique for Extending Delay and Slew Metrics for Ramp Inputs, C. Kashyap, C. J. Alpert, A. Devgan, F. Liu (IBM)
• Aggresive Crunching of Extracted RC Netlists, V. Rao (IBM)
• Efficient Switching Window Computation for Cross-talk Noise, B. Thudi, D. Blaauw (Michigan)
• Test Structures for Delay Variability, D. Boning (MIT)
• Performance Optimization of Single-Phase Level Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew, B. Taskin, I. Kourtev (Pittsburgh)

Back to Tau homepage