Tau 2025 Technical Program (draft)

[Invited] UPSET: SET Analysis and Optimization Flow for VLSI circuits based on Static Timing Analysis and Closed-loop IN-place Optimizations , Christos Sotiriou.
[Paper] In-Place Timing Optimisation Tool Flow for Asynchronous Circuits, Dimitrios Tsalapatas, Nikolaos Chatzivangelis, Christos P. Sotiriou and Nikolaos Sketopoulos.
[Paper] Fast and Accurate Glitch Propagation Modeling Using ANNs, Anastasis Vagenas, Dimitrios Garyfallou and George Stamoulis.

[Invited] Get rid of nonsens from optimization and analysis, Chirayu Amin.
[Panel] Sensitivity libraries and modeling special effects: Kevin Chen (TSMC), Ahmed Shebaita (Synopsys), Igor Keller (Cadence) (panel in preparation).

[Invited] Cryogenic computing, Michihiro Shintani (Invited, placeholder title)
[Paper] Compact Modeling for cryogenic-aware forward body biasing in 180nm Bulk CMOS, Zhipeng Liang, Shin Taniguchi, Hajime Takayama and Michihiro Shintani.
[Paper] Ternary logic operation of CMOS inverters under low-temperature and low-voltage conditions, Kotaro Tominaga, Ryosuke Matsuo, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani and Jun Shiomi.
[Invited] Applying static timing analysis techniques to novel superconducting logic families, Alex Braun (Cadence).

[Invited] IR-induced rail waveforms and their impact on timing, Ahmed Shebaita and Qian Shen (Invited, placeholder title)
[Paper] Analysis and Mitigation of IR-drop Induced Delay Effects Using Machine Learning, Megha Srinivas, Raj Shah, Omar Yamak, Ahmed Shebaita and Hamid Mahmoodi.

[Keynote]: Timing in Biological Neural Systems, Louis Scheffer.
Resource saving opportunities from standardization of holistic timing sign-off for energy-efficient Cloud silicon with Adaptive Voltage Scaling, Christian Lutkemeyer (Co-chair).
[Panel] Power integrity, AVS, and STA: Christian Lutkemeyer, Christian Sotiriou (panel in preparation).
[Planning] Future of Tau, Paul Pereira, Christian Lutkemeyer, Ahmed Shebaita.