TAU 2012 Power Grid Simulation Contest Announcement
The TAU 2012 Power Grid Simulation Contest was successfully held at TAU workshop. The contest details can be found here and the final presentation is here. We congratulate the winning teams for the TAU 2012 Power Grid Simulation Contest.
- First place award (2012): pgt_solver, University of Illinois at Urban-Champaign, T. Yu, Martin D. F. Wong
- Second place award (2012): PowerRush, Tsinghua University, J. Yang, Z. Li, Y. Cai, Q. Zhou
- Third place award (2012): IITPGS, Illinois Institute of Technology, X. Xiong, J. Wang.
You can find the 2011 Power Grid Simulation Contest here. The winning teams for 2011 contest are
- First place award (2011): PowerRush, Tsinghua University, J. Yang, Z. Li, Y, Cai, Q. Zhou, Y. Ma
- Second place award (2011): SEVA, National Tsinghua University, Missouri University of Science & Technology, S. Chang, C. Chou, C. Lee, S. Lin, Y. Shi, N. Tsai, H. Yu
- Third place award (2011): TicTac, Texas A& M University, Z. Zeng, T. Xu, P. Li
What’s New
Good News!
The final program has been posted. Please click PROGRAMS on the left for details.
The year of 2012 marks the 19th ACM/IEEE International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU'12 Workshop).
For the first time, TAU will be held outside of the US, i.e., it will be held in
National Taiwan University, Taiwan.
The dates are January 18-20, 2012.
TAU'12 will be featuring leaders from the industry and academia, who will present the
challenges they are facing and the current activities in their organizations. Domain
experts will lecture on topics that are of interest to the TAU community.
TAU'12 has already lined up a number of prominent leaders/visionaries from both the
industry and academia to speak at this forum. A sample list includes:
-
Dr. Tak Ning, IBM Fellow, IBM Thomas J. Watson Research Center
-
Dr Burn Lin, VP, TSMC
-
Dr. Chandu Visweswariah, Distinguished Engineer, IBM Corp.
-
Dr. Bing Sheu, Honorary Professor, National Taiwan University
-
Dr. Sani Nasif, Master Inventor, IBM Thomas J. Watson Research Center
-
Dr. Zhihong Liu, Board Chairman, ProPlus Design Solutions, Inc
-
Dr. Jiayuan Fang, CEO and Presdient, Sigrity, Inc
-
Dr. Vassilios Gerousis, Senior Architect & Technologist, Cadence Design Systems
-
Dr. Noel Menezes, Director, Intel Strategic CAD Labs
-
More to come...
The TAU 2012 Power Grid Simulation Contest was successfully held at TAU workshop. The contest details can be found here and the final presentation is here. We congratulate the winning teams for the TAU 2012 Power Grid Simulation Contest.
- First place award (2012): pgt_solver, University of Illinois at Urban-Champaign, T. Yu, Martin D. F. Wong
- Second place award (2012): PowerRush, Tsinghua University, J. Yang, Z. Li, Y. Cai, Q. Zhou
- Third place award (2012): IITPGS, Illinois Institute of Technology, X. Xiong, J. Wang.
If you are interested in
past year TAU events,
you can find it from here.
Presentation slides for TAU 2011 have been posted
in the
TAU 2011’ programs.
CALL FOR PAPERS - TAU 2012
CFP in PDF
The TAU series of workshops provide an informal forum for practitioners and researchers
working on temporal aspects of integrated circuits to disseminate early work and engage in a free
discussion of ideas.
TAU 2012 workshop invites submissions from all areas related to the timing properties of both digital and analog electronic systems, including but not limited to:
Transistor level models
Analog circuit modeling
Timing interfaces with mixed signal circuits
Reliability modeling and simulation
Circuit-level simulation of digital circuits
Simulation and characterization of SRAM circuits
Digital cell characterization for many corner/statistical timing
Timing-driven system design, synthesis and physical design
Sensitivity analysis
Full custom design analysis
Integrated functional-temporal analysis
Timing issues in low power design and testing
Power-delay trade-offs
Delay models and metrics
Layout impact on timing
Timing-driven layout optimization
Timing-driven synthesis and re-synthesis
Circuit optimization
Uncertainty-based analysis
Incorporation of manufacture impacts to timing
Reliability impact on performance
Process & environmental variation models
Statistical analysis technique
Clocking, synchronization, and skew
Clock domains, static/dynamic logic
Novel clocking and no-clock (Asynchronous) schemes
Timing implications of emerging technologies
IMPORTANT DATES
Submission deadline: Oct 1, 2011 Sunday 11:59 PM US EST, Oct 16, 2011
Acceptance notification: Nov 1, 2011
Camera-ready paper due: Nov 30, 2011
SUBMISSION OF PAPERS
All papers must be submitted electronically through
EasyChair.org.
Submissions are limited to 6 pages in the double column proceedings format.
In order to allow for a blind review, the submitted pdf version of the papers should
not contain the author name(s) or any direct reference(s)
to paper(s) from the same author(s).
TAU is a workshop aimed at fostering a high level of professional interaction,
not a conference. Copies of papers will be provided to the attendees, but the proceedings
will not be published by the ACM or the IEEE. Therefore, accepted papers can still be
submitted to other conferences and journals.
The intent of the workshop is to encourage the vigorous and unfettered discussion of the
latest ideas in the field.
WORKSHOP ORGANIZATION
General Chair: Charlie Chen, National Taiwan University,
cchen@cc.ee.ntu.edu.tw
Program Chair: Jinjun Xiong, IBM Research Center,
jinjun@us.ibm.com
Contest Chair: Zhuo Li, IBM Research Center,
lizhuo@us.ibm.com
TAU'12 Program Organization
General chair:
Charlie Chung-Ping Chen, National Taiwan University
TPC chair:
Jinjun Xiong, IBM Research Center
Contest chair:
Zhuo Li, IBM Research Center
TPC members:
Chirayu Amin, Intel Corp.
Shih-Chieh Chang, National Tsing Hua University
Debasish Das, Magma Design Automation
Satyendra Datla, Texas Instruments
Igor Keller, Cadence Design Systems
Iris Hui-Ru Jiang, National Chiao Tung University
Xin Li, Carnegie Mellon University
Jing-Jia Liou, National Tsing Hua University
Hidetoshi Onodera, Kyoto University
Dusan Petranovic, Mentor Graphics
Yiyu Shi, Missouri University of Science and Technoogy
Jun Tao, Fudan University
Wenjian Yu, Tsinghua University
Vladimir Zolotov, IBM Corp
SUBMISSION OF PAPERS
The submission deadline has past. All papers accepted have been notified to the contact author.
Now the submission website is opened to accept camera-ready final version.
Please follow this link to the
TAU submission website to upload your final version by Nov 30, 2011.
The final version must be in pdf format and in
LETTER size with no more than 6 pages.
Registration Information
| Early Registration (by December 15, 2011) |
On-site Regisration (after December 15, 2011) |
IEEE/ACM Members | $350 | $400 |
Non Members | $400 | $450 |
IEEE/ACM Student Members | $75 | $100 |
Refund Policy | Registrations canceled before December 15, 2011 will be refunded in full, less a $50 processing fee. No refunds will be issued after December 15, 2011. |
The on-line registration is handled by regonline.com.au. Please follow
this like to proceed,
or use the following URL: https://www.regonline.com/tau2012
If you need to have a Taiwan Visa to travel to Taiwan, please start the Visa application process ASAP,
as it may take longer than expected to get your Visa.
If you need an Invitation Letter for your Visa application, please contact
either Program Chair, Prof. Charlie Chung-Ping Chen, or TPC Chair, Dr. Jinjun Xiong, directly.
For more information about traveling to Taiwan and Visa issues related to your country, please
visit the Overseas Office, Republic of China (Taiwan).
Technical Program Information
Location
Barry Lam Hall
Graduate Institute of Electronics Engineering
National Taiwan University, Taipei, Taiwan, 10617, R.O.C.
January 17, 2012, Tuesday
7:00-9:00 pm, Reception for Invited Speakers at LivingOne
January 18, 2012, Wednesday
8:20-8:30 am, Welcome (Prof. Charlie Chen, TAU General Chair)
8:30-10:00 am, Invited Presentation
Mastering Nanometer Era with TSMC Open Innovation Platform
- Dr. Bing Sheu, Director of TSCM, Honorary Professor of National Taiwan University
On the Future of Silicon besides Scaling CMOS towards 10 nm
- Dr. Tak Ning, Fellow, IBM Research
Challenges and Advances in Delay Calculation and SI Analysis in Advanced Process Nodes
- Dr. Igor Keller, Cadence Design Systems
10:30-12:00 pm, Technical Paper Presentation: Statistical Timing Analysis
Timing Analysis with Nonseparable Statistical and Deterministic Variations
- Vladimir Zolotov, Debjit Sinha, Jeffrey Hemmett, Eric Foreman, Chandu Visweswariah, Jinjun Xiong,
and Jeremy Leitzen, IBM
Acceleration Scheme for Monte Carlo based SSTA using Generalized STA Processing Element
- Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, Kyoto University
Reversible Statistical max/min Operation: Theory and Applications to Timing
- Debjit Sinha, Chandu Visweswariah, Jinjun Xiong, Vladimir Zolotov, and Natesan Venkateswaran, IBM
1:00-2:30 pm, Invited Presentation
Timing Analysis and Physical Synthesis: Marriage Counseling in an Uneasy Relationship
- Dr. Patrick Groeneveld, Chief Technologist, Magma Design Automation
Facing Process Variation Challenges in IC Design
- Dr. Zhihong Liu, CEO, ProPlus Design Solutions, Inc
Timing Closure in the Era of Dominant Process Variations
- Dr. Satyendra Datla, Texas Instruments
2:45-4:15 pm, Technical Paper Presentation: Machine Learning, Information Theories, and Chaos expansion: How to Make Them Relevant?
Online Dynamic Power Management for Multicore Processors Using Reinforcement Learning
- Wan-Yu Lee and Iris Hui-Ru Jiang, National Chiao Tung University, Taiwan
An Information-theoretic Framework for Optimal Temperature Sensor Allocation and Full-chip Thermal Monitoring
- Huapeng Zhou, Xin Li, Chen-Yong Cher, Eren Kursun, Haifeng Qian, and Shi-Chune Yao, Carnegie Mellon University and IBM
A Dynamic Method for Efficient Random Mismatch Characterization of Standard Cells
- Wangyang Zhang, Amith Singhee, Jinjun Xiong, Peter Habitz, Amol Joshi, Chandu Visweswariah and James Sundquist, IBM
4:30-6:00 pm, Student Contest Paper Special Session
PowerRush: A Linear Simulator for Power Grid
- Jianlei Yang, Zuowei Li, Yici Cai and Qiang Zhou, Tsinghua University, China
On the Preconditioner of Conjugate Gradient Method: A Power Grid Simulation Perspective
- Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi and Shih-Chieh Chang, National Tsing Hua University and Missouri University of Science and Technology
Experiences of Designing a STA Engine in the PATMOS STA Contest
- Tien-Yu Kuo, Yu-Yi Liang, Shao-Huan Wang and Wai-Kei Mak, National Tsinghua University, Taiwan
7:00-9:00 pm, Banquet
January 19, 2012, Thursday
8:30-10:00 am, Invited Presentation
The Future of Timing: {Divide and Conquer}4
- Dr. Chandu Visweswariah, Distinguished Engineer and Senior Manager, IBM
Electrical Performance Assessment and Model Extraction of IO Interconnects
- Dr. Jiayuan Fang, CEO, Sigrity, Inc
Double patterning: challenges and possible solutions in extraction and signoff methodology
- Dr. Dusan Petranovic, Jim Falbo, and Nur-Kurt Karsilayan, Mentor Graphics
10:30-12:00 pm, Technical Paper Presentation: Novel Design Techniques
InTimeFix: A Low-Cost and Scalable Technique for In-Situ Timing Error Masking in Logic Circuits
- Feng Yuan and Qiang Xu, The Chinese University of Hong Kong
Efficient Retention Register Assignment for Power Gated Designs
- Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai and Shih-Chieh Chang
Slew Rate Aware Lower Power and More Robust Clock Tree Construction
- Yeh-Chi Chang, Chun-Kai Wang and Hung-Ming Chen, National Chiao Tung University
1:30-3:30pm, Invited Presentation
Limit of Lithography, Resolution, Depth of Focus, Overlay Accuracy, or Economy
CAD beyond Timing: the Next Frontier
- Dr. Noel Menezes, Director, Intel Strategic CAD Labs
Linking Resilience and Timing Analysis
- Dr. Sani Nassif, Master Inventor, IBM Research
3DIC Verification Challenges and Solutions in 2.5D and 3D Configurations
- Dr. Dusan Petranovic and Dr. Myron Lin, Mentor Graphics
4:00-5:00 pm, Technical Paper Presentation: 3D Design
On the Futility of Thermal Through-Silicon-Vias
- Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Jui-Hung Chien, Yiyu Shi and Shih-Chieh Chang, National Tsing Hua University and Missouri University of Science and Technology
NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs
- Tsung-Heng Wu, Pei-Yu Huang, Yu-Min Lee and Chi-Wen Pan
5:00-5:30 pm, Technical Paper Presentation: Contest Results
TAU 2012 Power Grid Simulation Contest Results Announcement
January 20, 2012, Friday
8:00-5:00 pm, Informal Workshop Discussion and Sight-seeing
Hotel and Travel Information
TAU will be hosted at
Barry Lam Hall
Graduate Institute of Electronics Engineering
National Taiwan University, Taipei, Taiwan, 10617, R.O.C.
TAU recommended hotel is
Leader Hotel, Taipei
No. 83, Sec. 4, Roosevelt Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-8369-2858
Fax: 886-2-8369-2859
E-mail: ntu@leaderhotel.com
The table below shows the hotel standard rate and TAU negotiated hotel rate.
Room Type | Room Rates |
Negotiated Rates |
Superior Single | NT$5,500+10% | NT$2,500 |
Superior Twin | NT$6,000+10% | NT$2,700 |
Deluxe Single | NT$6,000+10% | NT$2,900 |
Leader Suite | NT$10,000+10% | NT$4,000 |
Executive Suite | NT$15,000+10% | NT$5,000 |
To secure the conference negotiated hotel rate, please (1) choose the room type when you register
on-line at the webpage, and
(2) at the same time, send your choice to the General Chair, Prof. Charlie Chen
cchen@cc.ee.ntu.edu.tw for reservation.