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TAU 2014 |
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Santa Cruz Dream Inn Santa Cruz, California, USA |
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TAU 2014 |
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Santa Cruz Dream Inn Santa Cruz, California, USA |
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Sponsored by:
ANNOUNCEMENTS:
| Regular paper/TAU-20 submission deadline | December 13, 2013 |
| Panel proposal deadline | December 16, 2013 |
| Discounted $159.00/night hotel rate | February 14, 2014 |
Registration:
Please register at https://www.regonline.com/tau2014. Registration rates are listed in the tables below. A cancellation fee of US $35 will be charged if you cancel your registration by Februrary 26, 2014. There will be no refunds on or after February 26, 2014.| Registration Type | Early Rate (until February 14, 2014) | Late/On-site Rate (after February 14, 2014) |
| ACM/IEEE Member | $325 | $375 |
| Student | $200 | $225 |
| Non-member/Non-student | $375 | $425 |
Hotel Reservations
We highly encourage you to stay at Santa Cruz Dream Inn where TAU 2014 will be held.
The hotel is offering special discounted rate of $159.00/night for on room reservations until February 14, 2014.
To reserve by PHONE: Individuals may call Santa Cruz Dream Inn reservations department at 1-831-426-4330, Monday through Saturday from 8am-6pm. Please mention that you will be attending ACM TAU workshop (group code 1403ACM/TA ). The first night is due as a deposit at the time of reservation and the balance is to be paid at check out.
To reserve ONLINE: Reservations can be made online on the website at https://www.jdvhotels.com/hotels/california/central-coast-hotels/santa-cruz-dream-inn#
. On the opening page below Book Rental Reservations Online select "Group Code" option, enter 1403ACM/TA and follow the prompts from there to confirm reservation. Please contact Chirayu Amin or Igor Keller if help is needed.
Submission Site:
TAU 2014 is using Easy Chair to manage submissions. Submit final versions of your papers, TAU-20 talks, and panel proposals at https://www.easychair.org/conferences/?conf=tau2014.
Submission areas (do not limit yourself to this list)
| All levels (transistor, system, etc.) of timing analysis | Timing-driven synthesis and re-synthesis | |
| Timing-driven system design, synthesis and physical design | Circuit optimization | |
| Sensitivity analysis | Uncertainty-based analysis | |
| Full custom design analysis | Incorporation of manufacture impacts to timing | |
| Integrated functional-temporal analysis | Reliability impact on performance | |
| Timing issues in low power design and testing | Process & environmental variation models | |
| Power-delay trade-offs | Statistical analysis technique | |
| Delay models and metrics | Clocking, synchronization, and skew | |
| Layout impact on timing | Clock domains, static/dynamic logic | |
| Timing-driven layout optimization | Novel clocking and no-clock (Asynchronous) schemes | |
| Timing implications of emerging technologies |
TAU 2014 Program
Download the program in PDF format
Thursday, March 6, 2014
8:00 a.m. - 8:45 a.m. Breakfast
8:45 a.m. - 9:00 a.m. Opening Remarks
9:00 a.m. - 10:20 a.m. Timing For Analog and Mixed-Signal (Chair: Vladimir Zolotov, IBM)
Approximate property checking of mixed-signal circuits (slides)
Parijat Mukherjee1, Chirayu Amin2, Peng Li1
1 Texas A&M University, 2 Intel
An Exact Linear Time Algorithm for Computing Worst Case Eye Diagrams for a Class of Non-Linear High-Speed Signaling Systems (slides)
Aadithya Karthik, Sayak Ray, Robert Brayton and Jaijeet Roychowdhury (UC Berkeley)
Cell-based Physical Design Automation for Analog and Mixed Signal Application
Norihiro Kamae, Islam A.K.M Mahfuzul, Akira Tsuchiya and Hidetoshi Onodera (Kyoto University)
10:20 a.m. - 10:50 a.m. Break
10:50 a.m. - 12:10 p.m. Invited Session (Chair: Igor Keller, Cadence)
Horseshoes, Hand Grenades, and Timing Signoff: When Getting Close is 'Good Enough' (slides)
Anthony Hill, Arvind Nv and Krishna Panda (Texas Instruments)
Towards a Framework for 'Responsible Timing' (slides)
João Geada, (CLK Design Automation)
12:10 p.m. - 1:30 p.m. Lunch
1:30 p.m. - 3:10 p.m. Variability in Timing (Chair: Tom Spyrou, Altera )
Increasing the Accuracy of Interconnect Delay Derates: A Path Based Method (slides)
Ryan Kinnerk, Colm O'Doherty (Analog Devices), Emanuel Popovici (University College Cork)
Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation
Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera (Kyoto University)
Modeling Slew Dependent Constraint Arc Variation in Static Timing Analysis
Christian Lütkemeyer and Praveen Ghanta (Broadcom)
Timing Sign-off for Selective Voltage Binning (slides)
Vladimir Zolotov, Eric Foreman, Jeffrey Hemmett, Natesan Venkateswaran and Chandramouli Visweswariah (IBM)
3:10 p.m. - 3:30 p.m. Break
3:30 p.m. - 4:30 p.m. Hierarchical Timing (Chair: Qiuyang Wu, Synopsys)
Equivalency Checking for Timing Constraints (slides)
Subramanyam Sripada, Cho Moon, Loa Mize, Szu-Tsung Cheng and Sonia Singhal (Synopsys)
Sign Off Quality Hierarchical Timing Constraints: Wishful Thinking or Reality? (slides)
Oleg Levitsky (Cadence)
4:30 p.m. - 6:00 p.m. Panel: Library Characterization: A Cinderella Story?
Organizer & Moderator: Florin Dartu (TSMC) slides
Panelists: Federico Politi (Cadence, slides),
João Geada (CLK DA, slides), Nanda Gopal (Synopsys, slides),
Ramesh Kandadai (Intel, slides),
Tom Spyrou (Altera, slides), Jim Dodrill (ARM, slides)
7:00 p.m. - 9:00 p.m. Reception
Friday, March 7, 2014
8:00 a.m. - 8:45 a.m. Breakfast
8:45 a.m. - 9:15 a.m. TAU Timing Contest (slides)
Presenter: Jin Hu (IBM)
9:15 a.m. - 10:45 a.m. Testing and analysis of Analog/Mix-Signal Circuits (Chair: Florin Dartu, TSMC)
Probabilistic Bug Localization for Analog/Mixed-Signal Circuits using Probabilistic Graphical Models (slides)
Sangho Youn and Chenjie Gu (Intel)
ABCD-NL: Approximating Non-Linear Analog/Mixed-Signal Systems using Purely Boolean Models for High-speed Simulation and Formal Verification (slides)
Aadithya Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert Brayton and Jaijeet Roychowdhury (UCB)
Trace-based fault localization with supply voltage sensor (slides)
Miho Ueno, Masanori Hashimoto and Takao Onoye (Osaka University)
10:45 a.m. - 11:00 a.m. Break
11:00 a.m. - 12:10 p.m. Challenges for STA in Advance Process Nodes (Chair: Christian Lütkemeyer, Broadcom)
Timing analysis comprehending mask misalignment due to Double Patterning (slides)
Arvind Nv and Ajoy Mandal (Texas Instruments)
A Slew/Load-Dependent Approach to Single-Variable Statistical OCV Modeling (slides)
Brandon Bautz and Swamy Lokanadham (Cadence)
Challenges in Static Timing Analysis with FinFET
King Ho Tam, Florin Dartu, Tzu-Hen Lin and Tai-Yu Cheng (TSMC)
12:10 p.m. - 12:40 p.m. Lunch
12:40 p.m. - 2:40 p.m. Panel: What's the Next Big Timing Signoff Challenge?
Organizers: Arvind Nv, Anthony Hill, Krishna Panda, Ajoy Mandal (Texas Instruments)
Moderator: Anthony Hill (Texas Instruments)
Panelists: Vladimir Zolotov (IBM), Ruben Molina (Cadence), Hashimoto Masanori (Osaka University),
Christian Lütkemeyer (Broadcom), Alireza Kasnavi (Synopsys), Krishna Panda (TI)
Organizers:
General Chair: Chirayu Amin , Intel Corporation,
Technical Program Chair: Igor Keller , Cadence,
Contest Committee: