TAU 2013

TAU 2013

Co-located with ISPD 2013

March 27–29, 2013
Ridge Tahoe Resort (Lake Tahoe)
Stateline, Nevada, USA


Sponsored by: Association for Computing Machinery Cadence IBM Intel Synopsys


  1. [Mar-11-2013, 12:00 PM US PDT] TAU 2013 PROGRAM has been finalized now and is posted below. Panel on SSTA has been moved to Thursday and there are some changes to session and break/lunch timings.
  2. [Jan-26-2013, 2:30 PM US PST] REGISTRATION is now open at https://www.regonline.com/tau2013. Register by March 2, 2013, to get a discount.
  3. [Oct-16-2012, 11:22 AM US PDT] TAU 2013 CAD Contest (Variation Aware Timing Analysis) is open. Please visit https://sites.google.com/site/taucontest2013/ for details.

TAU 2013 Program

Download the program in PDF format

Wednesday, March 27, 2013

11:00 a.m. – 12:00 p.m. TAU/ISPD Joint Session on Contests (Chair: Charles Liu, TSMC)

The ISPD 2013 Discrete Gate Sizing Contest and Benchmark Suite
Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven Burns, Gustavo Wilke, Cheng Zhuo (Intel)

The TAU 2013 Variability Aware Timing Analysis Contest
Debjit Sinha1, Luis Guerra e Silva2, Jia Wang3, Shesha Ragunathan1, Dileep Netrabile1, Ahmed Shebaita4
1IBM, 2INESC-ID / IST - TU Lisbon (Portugal), 3Illinois Institute of Technology, 4Synopsys

12:10 p.m. – 1:30 p.m. TAU/ISPD Keynote and Lunch (Chair: Chirayu Amin, Intel)
Opportunities and Challenges for High Performance Microprocessor Designs and Design Automation
Dr. Ruchir Puri (Fellow, IBM)
Abstract Slides

1:30 p.m. – 1:45 p.m. Break

1:45 p.m. – 2:00 p.m. TAU 2013 Opening remarks by Jinjun Xiong (IBM), TAU General Chair

2:00 p.m. – 3:30 p.m. TAU/ISPD Invited Session: What will it take to tame the hierarchical design trolls? (Chair: Tom Spyrou, Altera)

To do or not to do Hierarchical Timing? (Chair: Tom Spyrou, Altera)
Florentin Dartu and Qiuyang Wu (Synopsys)

Variability Aware Hierarchical Implementation of Big Chips
Vidyamani Parkhe (Mentor Graphics)

Challenges in Managing Timing and Wiring Contracts during Hierarchical Floorplanning and Design Closure
Shyam Ramji (IBM)

3:30 p.m. – 4:00 p.m. Break

4:00 p.m. – 5:30 p.m. EDA Court: Hierarchical Construction and Timing Sign-Off of SoCs
Judge: Chandu Visweswariah (IBM)
Plaintiffs: Amit Shaligram (ST Microelectronics), Guntram Wolski (Cisco), Larry Brown (IBM)
Defendants: Alex Rubin (IBM), Alexander Skourikhin (Intel), Oleg Levitsky (Cadence), Qiuyang Wu (Synopsys)

6:30 p.m. – 7:30 p.m. Hors D’oeuvres (Appetizers)

Thursday, March 28, 2013

8:30 a.m. – 9:00 a.m. Breakfast

9:00 a.m. – 10:30 a.m. Analog and Mixed Signal CAD (Chair: Duaine Pryor, Mentor Graphics)

Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data
Fa Wang1, Wangyang Zhang1, Shupeng Sun1, Xin Li1, Chenjie Gu2
1Carnegie Mellon University, 2Intel

A Formal Approach to DC Operating Point Analysis for Large Mixed Signal Circuits: Challenges and Opportunities
Parijat Mukherjee1, Chirayu Amin2, Peng Li1
1Texas A&M University, 2Intel

ABCD-D: Accurately Capturing Analog Effects in Digital Components using Finite State Machine Models
Karthik Aadithya, Jaijeet Roychowdhury (University of California, Berkeley)

10:30 a.m. – 11:00 a.m. Break

11:00 a.m. – 12:00 p.m. Panel: Variability in Timing: Where is Statistical Timing?
Organizer and Moderator: Igor Keller (Cadence)
Panelists: Anthony Hill (Texas Instruments), Debjit Sinha (IBM), Florentin Dartu (Synopsis), Hidetoshi Onodera (Kyoto University)

12:00 p.m. – 1:30 p.m. Lunch

1:30 p.m. – 2:30 p.m. Keynote (Chair: Chirayu Amin, Intel)
Unsolved Problems in Static Timing Analysis: A Challenge
Tom Spyrou (Design Technology Architect, Altera)
Abstract Slides

2:30 p.m. – 3:30 p.m. TAU-20 Talks (Chair: Hidetoshi Onodera, Kyoto University)

Signal Integrity Analysis in 20nm and Below: Challenges and Advances
Igor Keller (Cadence)

Multi-synchronous Approaches to Derive Energy and Architectural Benefits in Clocked Peripherals
William Lee, Vikas Vij, Dipanjan Bhadra, Ken Stevens (University of Utah)

Construction of a Timing-Driven Variation-Aware Global Router with Concurrent Multi-Net Congestion Optimization
Radhamanjari Samanta1, Soumyendu Raha1, Adil Erzin2
1Indian Institute of Science (Bangalore), 2Sobolev Institute of Mathematics (Russian Academy of Sciences, Novosibirsk, Russia)

3:30 p.m. – 4:00 p.m. Break

4:00 p.m. – 5:30 p.m. Variability and Uncertainty (Chair: Peng Li, Texas A&M University)

An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera (Kyoto University, Japan)

Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty
Takashi Matsumoto1, Kazutoshi Kobayashi2, Hidetoshi Onodera1
1Kyoto University (Japan), 2Kyoto Institute of Technology (Japan)

Multiple Input Switching and Variability-aware Gate Delay Modeling for Ultra-Low Power CMOS Circuits
Prasanjeet Das, Sandeep Gupta (University of Southern California, Los Angeles)

6:30 p.m. – 8:30 p.m. Dinner and Discussion with Past TAU Chairs
Talk by Rick McGeer (General Chair of first TAU)

Friday, March 29, 2013

8:30 a.m. – 9:00 a.m. Breakfast

9:00 a.m. – 10:30 a.m. Statistical Analysis (Chair: Debjit Sinha, IBM)

Eagle-Eye: A Near-Optimal Statistical Framework for Noise Sensor Placement
Tao Wang1, Chun Zhang1, Yiyu Shi1, Jinjun Xiong2
1Missouri University of Science and Technology, 2IBM

Speeding up Computation of the max/min of a set of Gaussians for Statistical Timing Analysis and Optimization
Vimitha Kuruvilla1, Debjit Sinha1, Jeff Piaget1, Chandu Visweswariah1, Nitin Chandrachoodan2
1IBM, 2Indian Institute of Technology (Chennai, India)

Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations
André Lange1, Roland Jancke1, Joachim Haase1, Ingolf Lorenz2, Ulf Schlichtmann3
1Fraunhofer-Institue for Integrated Circuits, 2Global Foundries, 3Technische Universitäat München (Germany)

10:30 a.m. – Closing remarks

11:00 p.m. – 12:00 p.m. Lunch

The TAU workshop is a highly interactive and engaging annual gathering of experts in electronic design automation (EDA) of timing, physical, power, electrical, and functional analysis and validation of digital and analog circuits and systems. We invite you all to join us at TAU 2013 to discuss and debate novel ideas and to lead creation of the next generation of EDA tools and methods. Find out what’s hot today and where in EDA research would people like to place their money and resources.

Important Dates:

Discounted $99.00/night hotel rateFebruary 23, 2013


Please register at https://www.regonline.com/tau2013. Registration rates are listed in the tables below. A cancellation fee of US $35 will be charged if you cancel your registration by March 2, 2013. There will be no refunds on or after March 3, 2013.

TAU (joint sessions with IPSD are included):

Registration TypeEarly Rate
(until March 2, 2013)
Late/On-site Rate
(after March 2, 2013)
ACM/IEEE Member$350$400


Registration TypeEarly Rate
(until March 2, 2013)
Late/On-site Rate
(after March 2, 2013)
ACM/IEEE Member$680$780

Hotel Reservations

We highly encourage you to stay at Ridge Tahoe Resort where TAU will be held along with ISPD. The hotel is offering special discounted rate of $99.00/night for on room reservations until February 23, 2013.

To reserve by PHONE: Individuals may call Ridge Tahoe Resort reservations department at 1-800-334-1600, Monday through Saturday from 8am-6pm. Please mention that you will be attending ACM TAU workshop (promo code ACM2013). The first night is due as a deposit at the time of reservation and the balance is to be paid at check out.

To reserve ONLINE: Reservations can be made online on our website at www.ridgetahoeresort.com. On the opening page below Book Rental Reservations Online enter the promo code ACM2013 and follow the prompts from there to confirm a reservation.

Submission Site:

TAU 2013 is using Easy Chair to manage submissions. Submit final versions of your papers, TAU-20 talks, and panel proposals at https://www.easychair.org/conferences/?conf=tau2013.


General Chair: Dr. Jinjun Xiong, IBM Thomas J. Watson Research Center, IBM Corporation
Technical Program Chair: Dr. Chirayu Amin, Strategic CAD Lab, Intel Corporation
Contest Chair: Dr. Debjit Sinha, IBM Corporation

Technical Program Committee:

Sponsored by Association for Computing Machinery (ACM) SIGDA, Cadence, IBM, Intel, and Synopsys