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TAU 2015

ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

March 12-13, 2015 - Monterey, California
www.tauworkshop.com

Important dates

Invited paper submission: Closed
Paper submission deadline (now closed): Nov 26, 2014
Acceptance notification: Dec 22, 2014
Camera ready paper due (for accepted papers): Jan 12, 2015

Call for papers [PDF] [TXT]

What is the future of timing analysis? How to meet the industry’s insatiable quest for speed, capacity, accuracy, and integration with optimization? Will parallelism be the final answer, or shall we fundamentally re-think timing? What about the challenges for process, 3D, variability, analog modeling and validation?

The TAU series of workshops provide an informal forum for practitioners and researchers working on these and other temporal aspects of analog and digital systems to disseminate early work and engage in a free discussion of ideas. The twenty-second in the TAU series, the TAU 2015 workshop invites submissions and proposals from the traditional as well as emerging areas related to the timing properties of digital electronic systems, including but not limited to the topics listed below.

Timing (including incremental timing)
• System-level timing
• Circuit/gate-level timing
• Transistor-level timing
• Timing of mixed signal circuits
• Common path pessimism removal/reduction
Modeling and simulation
• Transistor level modeling
• Analog circuit modeling
• Circuit level simulation
• Delay models and metrics
• Reliability modeling and simulation
Variability
• Timing analysis under uncertainty
• Statistical timing analysis and optimization, Monte Carlo and stochastic methods
• Variation modeling
• Digital cell characterization for many corner/statistical timing
• Sensitivity/criticality analysis
• Yield analysis and optimization
Power, trade-offs and optimization
• Timing issues in low-power design
• Power-delay tradeoffs
• Layout impact on timing
• Timing driven layout optimization
• Timing driven synthesis, re-synthesis
• Circuit optimization
Signal integrity
• Crosstalk modeling, analysis, avoidance and optimization
• Adjacent line switching and coupling
Clocking
• Clocking, synchronization, and skew
• Clock domains, static/dynamic logic
• Novel clocking schemes
Characterization
• Cell (library) characterization
• Latch characterization
• Simulation and characterization of SRAM circuits
Hierarchical timing
• Timing macro-modeling
• Incorporating crosstalk and/or variation effects in macro-modeling
Emerging technologies
• Full custom design analysis
• Special circuit families
• Timing issues for 3D ICs
• Modeling and analysis of TSVs
• Timing implications of emerging technologies
Others
• Integrated functional-temporal analysis
• Formal theories and methods
• Asynchronous systems
• Smart sensor placement

Submission of papers

All papers (including invited papers) must be submitted electronically using the EasyChair system using the link under the Logistics tab.

Submissions are limited to 6 pages in the double column proceedings format (prefered). In order to allow for a blind review of non-invited papers, submitted pdf version (required) of the papers should not contain the authors name or any direct reference to the authors. TAU is a workshop aimed at fostering a high level of professional interaction, not a conference. Copies of papers will be provided to the attendees, but the proceedings will not be published by the ACM or the IEEE. Therefore, accepted papers can still be submitted to other conferences and journals.