Registration is Open!

Register online through Cvent.

Book your room at the beautiful Embassy Suites by Hilton Monterey Bay Seaside with a discounted Tau ‘25 rate of $199. The discounted rate is available until April 21st, 2025.

Hotel: Embassy Suites by Hilton Monterey Bay Seaside
Address: 1441 Canyon Del Rey Blvd, Seaside, CA 93955
Phone: (831) 393-1115 Tau ‘25 hotel rate: $199

TAU registration prices

Regular - now to April 9th	$540
Regular - after April 9th	$550
Student - now to April 9th	$265
Student - after April 9th	$275

Thursday, May 1st, 2025

Breakfast

• [7:30] Breakfast buffet for hotel guests, $20 for visitors

Opening remarks

• [8:30] Remarks from the General Chair, Paul Pereira (Qualcomm)
• [8:35] Why Tau and Timing Sign-off matters! Christian Lutkemeyer, Technical Chair (PIX-EDA)

Session on IR-induced Delay

• [8:45, Invited] IR-induced rail waveforms and their impact on timing, Ahmed Shebaita and Brett Yokom (Invited, placeholder title)
• [9:30, Paper] Analysis and Mitigation of IR-drop Induced Delay Effects Using Machine Learning, Megha Srinivas, Raj Shah, Omar Yamak, Ahmed Shebaita and Hamid Mahmoodi.

Break

• [10:00] Coffee and tea

Session on Glitches, Soft errors, and Asynchronous Circuits

• [10:15, Invited] UPSET: SET Analysis and Optimization Flow for VLSI circuits based on Static Timing Analysis and Closed-loop IN-place Optimizations , Christos Sotiriou.
• [11:00, Paper] In-Place Timing Optimisation Tool Flow for Asynchronous Circuits, Dimitrios Tsalapatas, Nikolaos Chatzivangelis, Christos P. Sotiriou and Nikolaos Sketopoulos.
• [11:30, Paper] Fast and Accurate Glitch Propagation Modeling Using ANNs, Anastasis Vagenas, Dimitrios Garyfallou and George Stamoulis.

Lunch

• [12:00] Plated lunch

Session on Superconducting and Cryogenic Computing

• [1:00, Invited] Transistor Model Development for Cryo-IC Design Environment, Michihiro Shintani.
• [1:45, Paper] Compact Modeling for cryogenic-aware forward body biasing in 180nm Bulk CMOS, Zhipeng Liang, Shin Taniguchi, Hajime Takayama and Michihiro Shintani.
• [2:15, Paper] Ternary logic operation of CMOS inverters under low-temperature and low-voltage conditions, Kotaro Tominaga, Ryosuke Matsuo, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani and Jun Shiomi.
• [2:45, Invited] Applying static timing analysis techniques to novel superconducting logic families, Alex Braun (Cadence).

Break

• [3:30] Snack

Session on Sensitivity Libraries and Modeling Special Effects

• [3:45, Invited] Get rid of nonsens from optimization and analysis, Chirayu Amin.
• [4:30, Panel] Margin or Model - can you have your cake and eat it too? Florin Dartu (TSMC), Li Ding (Synopsys), Chirayu Amin (Cadence), Checkad Anvar (Broadcom), Christian Seo (Samsung), Benny Widen (Nvidia), moderated by Igor Keller (Cadence).
• [5:30] Adjournment

Reception and dinner

• [6:30] Reception
• [7:30] Dinner

Friday, May 2nd, 2025

Breakfast

• [7:30] Breakfast buffet for hotel guests, $20 for visitors

Opening remarks

• [8:30] Opening remarks

Keynote

• [8:35, Keynote]: Timing in Biological Neural Systems, Louis Scheffer.

AVS and power integrity

• [9:15, Standardization] AVS Anchor Seminar (Part 1), Christian Lutkemeyer (Co-chair).

Break

• [10:00] Coffee and tea

AVS and power integrity (cont.)

• [10:15] AVS Anchor Seminar (Part 2), Christian Lutkemeyer (Co-chair).
• [11:00, Panel] Power integrity, AVS, and STA: Christian Lutkemeyer (PIX-EDA), Christian Sotiriou (U. Thessaly), Massoud Ghahroodi (Broadcom), Brett Yokom (Ansys).

Lunch

• [12:00] Box lunch

Planning and Closing Remarks

• [1:00] Future of Tau, Paul Pereira, Christian Lutkemeyer, Ahmed Shebaita.
• [1:30] Workshop closes.

Important dates

• Paper submission deadline: Feb 11, 2025 (Monday)
• Acceptance notification: Feb 24, 2025 (Monday)
• Final paper submission: Mar 1, 2025 (Saturday)

It has become clear that timing analysis is NO longer a solved problem. So, what are new challenges as the industry embraces 5/3/2nm and below, rides the wave of ultra-low-power mobile, wearable devices and jumps on the IoT bandwagon? Are there new issues with older nodes, 14/28nm and up, in new design use cases? How do we model timing/power interactions? How do reliability requirements coming from ADAS/IoT and related impact timing? How to we apply AI/ML/Data Science techniques to the timing domain? How do we meet the insatiable demands for accuracy, performance and functionality? What new fundamental challenges are coming from process physics, 3D, variability, voltage sensitivity, analog effects, Quantum circuit modeling, Ising Models, Mixed signal modeling and validation?

It has become clear that timing analysis is NO longer a solved problem. So, what are new challenges as the industry embraces 5/3/2nm and below, rides the wave of ultra-low-power mobile, wearable devices and jumps on the IoT bandwagon? Are there new issues with older nodes, 14/28nm and up, in new design use cases? How do we model timing/power interactions? How do reliability requirements coming from ADAS/IoT and related impact timing? How to we apply AI/ML/Data Science techniques to the timing domain? How do we meet the insatiable demands for accuracy, performance and functionality? What new fundamental challenges are coming from process physics, 3D, variability, voltage sensitivity, analog effects, Quantum circuit modeling, Ising Models, Mixed signal modeling and validation?