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TAU 2018

ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

March 15-16, 2018
Monterey, California

TAU 2018 timing contest topic:
K critical paths with correct CRPR for all K paths
[Contest website]

The increase in the size of modern chip designs is forcing a paradigm shift from a traditional "flat timing" model to a "hierarchical timing" model. In the new paradigm, designs may be hierarchically partitioned into sub-blocks (or macros) that are timed in isolation (out-of-context), followed by a generation of a simplified timing macro-model that is plugged at the parent level of hierarchy. This aditionally enables re-use of macros and a parallel chip design and optimization environment.


The TAU 2017 contest will continue extend the coverage on the concept of hierarchical timing via timing macro-models. Modeling efficiency is the emphasied among manyother challenges during timing macro-modeling techniques. The goals of this year's TAU contest are:

  • increase awareness of timing analysis and need for timing macro-modeling;
  • encourage parallel (multithreaded, distributed) approaches;
  • introduce different macro-models and formats, including black-box and gray-box models, encapsulated in industry-standard formats;
  • create an evaluation environment to measure the performance of macro-modeling generation and usage in terms of memory, runtime, and accuracy; and
  • facilitate a unified academic timing engine in which macro-models are generated and its quality is automatically compared to the original flat-timed design.

The winners of TAU 2017 timing Contests were

Prior year contests