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TAU 2018 Technical Program

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[Mar 15, 2018] [Mar 16, 2018] [PDF]

Program Details *

Thursday, March 15, 2018

8:00 a.m. – 9:00 a.m. Breakfast

9:00 a.m. – 9:15 a.m. Opening Remarks from general chair
 

9:15 a.m. – 10 a.m. Variation-Tolerant Adaptive and Resilient Designs in Nanoscale CMOS [Keynote] (Chair: Tom Spyrou, Intel) Speaker: Vivek De (Intel)

10:00 a.m. – 10:20 a.m. Break

10:20 a.m. – 11:00 a.m. Distributed Analysis (Chair: Kelvin Le, Intel)

• DtCraft: A Distributed Execution Engine for Compute-intensive Applications
  Tsung-Wei Huang, Chun-Xun Lin and Martin Wong (University of Illinois at Urbana-Champaign)
   
• Practical Distributed Timing Analysis: A case study on real world designs
  Anshuman Seth and Ulhas Kotha (NVIDA)
   

11:00 a.m. – 11:45 a.m. DvD impact on timing and taking advantage of timing information to optimize power grid design [Invited] (Chair: Qiuyang Wu, Synopsys) Speaker: Joao Geada (Ansys)

11:45 a.m. – 2 p.m. Lunch and social networking

2 – 2:45 p.m. Advances in the use of Graph Databases to Aid in the Timing Analysis of the World's Fastest Microprocessors [invited] (Chair: Song Chen, Synopsys) Speaker: Kerim Kalafala (IBM)

2:45 a.m. – 4:05 p.m. Variation Aware Timing Analysis (Chair: João Geada, Ansys)

• Via Resistance Variation-Aware Static Timing Analysis
  Moon Su Kim, Nathaniel Conos (Samsung), Kelvin Le and Hanif Fatemi (Synopsys)
   
• Analytical Approach to Statistical Logic Cell Delay Analysis and its Extension to a Timing Graph
  Dimitri Mishagli, Elena Blokhina and Tom Brazil (University College Dublin)
   
• QCSAIL - Quantile Computation via Sensitivity Analysis and Incremental Learning
  Rahul Krishnan, Dimitrios Stamoulis and Florentin Dartu (TSMC)
 
• GENERALIZED MOMENT BASED FRAMEWORK FOR ACCURATE AND EFFICIENT SSTA
  Ahmed Shebaita, Kelvin Le and Li Ding (Synopsys)

4:05 p.m. – 4:30 p.m. Break

4:30 p.m. – 6:00 p.m. Panel: Machine learning - Confluence with timing and EDA
Organizer: Debjit Sinha (IBM)

• Arun Venkatachar (Synopsys)
• Florin Dartu (TSMC)
• Kerim Kalafala (IBM)
• Richard Phillips (nVidia)
• Shiva Raja (Cadence)
• Shaan Awasthi (Intel)

7:00 p.m. – 9:00 p.m. Reception

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Friday, March 16, 2017

8:00 a.m. – 9:00 a.m. Breakfast

9:00 a.m. – 9:15 a.m. Opening Remarks from technical program chair

9:15 a.m. – 10:00 a.m. Make STA Accurate and Great Again! An in depth discussion of accuracy and runtime trade-offs [Keynote] (Chair: Tom Spyrou, Intel) Speaker: Igor Keller (Cadence)

10:00 a.m. – 10:40 a.m. Voltage Scaling Analysis (Chair: Christian Lutkemeyer, inPhi)

• Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors
  Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera (Kyoto University)
   
• Timing Margin of Multi Voltage Paths of FPGA
  Jignesh Shah (Intel)
   

10:40 – 11 a.m. Break

11 – 11:45 a.m. TAU contest: Efficient generation of timing reports from an STA graph with updated arrival and required times (Chair: Song Chen (Synopsys))
Presenters: George Chen (Intel)

11:45 a.m. – 2:00 p.m. Lunch and social networking

2:00 p.m. – 2:45 p.m. Software Acceleration with FPGA co-processing? [Invited] (Chair: Prasanjeet Das, Cadence) Speaker: David Munday (Intel)

2:45 p.m. – 3:25 p.m. Macro Modeling and Machine Learning ( (Chair: Oscar Ou, MediaTek)

• A Highly Compressed Timing Macro-modeling Algorithm for Large Scale Hierarchical and Incremental Timing Analysis
  Tin-Yin Lai and Martin D F Wong (University of Illinois at Urbana-Champaign)
   
• Use of Machine Learning Techniques for Testing Delay Calculators in FPGA Architectures
  Madhu Raman, Nizar Abdallah and Julien Dunoyer (MicroSemi)
   

3:25 p.m. – 4:00 p.m. Closing remarks & logistics

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