TAU 2020 timing contest topic:
Delay calculation using current models
[Contest
website]
With 45 nano meter and below process technology node, impact wire resistance & miller capacitance on circuit delay are non-ignorant. So, delay calculation using voltage based model like Non Linear Delay Model (aka NLDM) could not be accurate for some of the designs which are manufactured in 45 nm and below process technology node. To overcome these challenges, EDA vendors have proposed new timing models, Current Source Model (aka CSM). Static Timing Analysis (aka STA) tools require new methods for delay calculation using CSM. Most of the commercial STA tools can do timing analysis using current source model but none of the open source STA tool have that capability yet.
Contest results
And the winners are:- The TimeKeepers, University of Thessaly
- iTimer, National Taiwan University
Prior year contests
- 2019: Design Optimization
- 2018: Timing reports
- 2017: Timing Macro-Modeling part 2
- 2016: Timing Macro-Modeling
- 2015: Incremental timing and CPPR
- 2014: Common path pessimism removal (CPPR)
- 2013: Variation aware timing
- 2012: Power grid simulation
- 2011: Power grid simulation
