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TAU 2020 Technical Program

[Thursday, March 19th 2020] [Friday, March 20th 2020]

Program Details *(not final)

Thursday, March 19th, 2020

8:00 a.m. – 9:00 a.m. Breakfast

9:00 a.m. – 9:10 a.m. Opening Remarks from general chair
 

9:10 – 10:00 ASTA for Cyclic and Asynchronous Circuits [Keynote] (Chair: Paul Pereira) Speaker: Christos Sotiriou (University of Thessaly)

10:00 a.m. – 11:00 a.m. Advances in the Timing of Cyclic and Asynchronous Circuits (Chair: Ken Stevens)

• Cyclone: A fast static timing analysis engine for asynchronous circuits
  Rajit Manohar, Wenmian Hua, Yi-Shan Lu, and Keshav Pingali
   
• STA for Mixed Cyclic, Acyclic Circuits
  Stavros Simoglou, Dimitris Valiantzas, Nikolaos Sketopoulos, and Christos Sotiriou
   
• An Efficient Algorithm for Logic Replication for FPGAs Accounting for Combinational Loops
  Rupesh Shelar
   

11:00 p.m. – 11:15 p.m. Break

11:15 a.m. – 12:00 p.m. Probabilistic Models for Timing and Yield (Chair: Subra Sripada)

• Statistical timing analysis considering multiple-input switching
  Debjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael Wood, Jeffrey Hemmett, Suriya Skariah and Patrick Williams
   
• Sample-Based Statistical STA as a Foundation of Design Robustness Analysis and Optimization
  Igor Keller
   

12:00 p.m. – 1:45 p.m. Lunch

1:45 p.m. – 2:15 p.m. Simultaneous Multi Voltage Analysis with Dynamic Voltage Frequency Scaling [Invited] (Chair: Paul Pereira) Speaker: Paul Berevoescu (Synopsys)

2:15 p.m. – 2:45 p.m. Robust Rare Circuit Failure Detection using Data-Efficient Machine Learning [Invited] (Chair: Igor Keller) Speaker: Peng Li (University of California Santa Barbara)

2:45 p.m. – 3:00 p.m. Break

3:00 p.m. – 4:30 p.m. Panel on Parametric Yield
Organizer: Christian Lutkemeyer (Inphi)

• Srinivas Bodapati (Intel)
• Igor Keller (Cadence)
• Kelvin Le (now at Google)
• Paul Pereira (Qualcomm)
• Peivand Tehrani (Synopsys)

Friday, March 20, 2020

8:00 a.m. – 9:00 a.m. Breakfast

9:00 a.m. – 9:05 a.m. Opening Remarks from technical program chair

9:05 – 9:50 The OpenROAD Project : Goals, Demo, and Code Organization [Keynote] (Chair: Qiuyang Wu) Speaker: Tom Spryou

9:50 a.m. – 10:10 a.m. Break

10:10 a.m. – 11:30 a.m. TAU contest on Current Source Models (Chair: Jignesh Shah, Intel)
Presenter: George Chen (Intel)

• Introduction
• Contest winners' short presentations
• Contest results
• Award Ceremony

11:30 a.m. – 1:00 p.m. Lunch and social networking

1:00pm – 1:45pm Future of Simulation-Based Product Innovation in the Digital World [Keynote] (Chair: Debjit Sinha, IBM) Speaker: Prith Banerjee (Ansys)

1:45 p.m. – 2:45 p.m. Timing Analysis at Scale (Chair: Peivand Tehrani, Synopsys)

• Technology lookup table-based default timing assertions for hierarchical timing closure
  Ravi Ledalla, Debjit Sinha, Adil Bhanji, Chaobo Li, Gregory Schaeffer, Hemlata Gupta and Jennifer Basile
   
• Hierarchical Timing Constraints
  Subramanyam Sripada, Qiuyang Wu and Chang Zhao
   
• Architecture For Ordered Write Of Data Collected In Parallel For Path Based Report
  Anshul, Prabhat Maurya, and Shesha Raghunathan
   

2:45 p.m. – 3:00 p.m. Break

3:00 p.m. – 3:30 p.m. Aging Timing Signoff Solutions for Automotive and IoT Applications (Global Foundries) [Invited] (Chair: Paul Pereira) Speaker: Siddharth Sawant

3:30 p.m. – 4:00 p.m. On-premise and AWS Cloud Enablement of Xilinx Design Capture and Closure Flows using Ansys Path FX [Invited] (Chair: Joao Geada) Speakers: Simon Burke and Nitin Navale

4:00 p.m. – 4:30 p.m. Efficient Parasitic Interconnect Insertion for Timing Analysis [Invited] (Chair: Joao Geada) Speaker: Prof. Ron A. Rohrer (Southern Methodist University)

4:30 p.m. – 4:45 p.m. Closing remarks & logistics

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Site last updated: January 30, 2020 [Updates marked with *]