Technical program
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TAU 2020

ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

March 19 - 20, 2020
Monterey, California
www.tauworkshop.com

TAU 2020 Technical Program

[Thursday, March 19th 2020] [Friday, March 20th 2020]


Program Details *(not final)

Thursday, March 19th, 2020

8:00 a.m. – 9:00 a.m. Breakfast

9:00 a.m. – 9:10 a.m. Opening Remarks from general chair
 
9:10 – 10:00 ASTA for Cyclic and Asynchronous Circuits [Keynote] (Chair: Paul Pereira)
Speaker: Christos Sotiriou (University of Thessaly)

10:00 a.m. – 11:00 a.m. Advances in the Timing of Cyclic and Asynchronous Circuits (Chair: Ken Stevens)

11:00 p.m. – 11:15 p.m. Break

11:15 a.m. – 11:40 p.m. Probabilistic Models for Timing and Yield (Chair: Subra Sripada) 11:40 a.m. – 1:00 p.m. Lunch
1:00 p.m. – 1:45 p.m. Process Related Challenges in Timing Signoff and Directions to Solve them [Invited] (Chair: Joao Geada)
Speaker: Kevin Chen (TSMC)

1:45 p.m. – 2:15 p.m. Simultaneous Multi Voltage Analysis with Dynamic Voltage Frequency Scaling [Invited] (Chair: Paul Pereira)
Speaker: Paul Berevoescu (Synopsys)

2:15 p.m. – 2:45 p.m. Robust Rare Circuit Failure Detection using Data-Efficient Machine Learning [Invited] (Chair: Igor Keller)
Speaker: Peng Li (University of California Santa Barbara)

2:45 p.m. – 3:15 p.m. A Timing Methodology for Metal Variation [Invited] (Chair: Paul Pereira)
Speaker: Chul Rim (Samsung)

3:15 p.m. – 3:30 p.m. Break

3:30 p.m. – 5:00 p.m. Panel on Parametric Yield
Organizer: Christian Lutkemeyer (Inphi)

Friday, March 20, 2020

8:00 a.m. – 9:00 a.m. Breakfast

9:00 a.m. – 9:05 a.m. Opening Remarks from technical program chair
9:05 – 9:50 The OpenROAD Project : Goals, Demo, and Code Organization [Keynote] (Chair: Qiuyang Wu)
Speaker: Tom Spryou

9:50 a.m. – 10:10 a.m. Break


10:10 a.m. – 11:30 a.m. TAU contest on Current Source Models (Chair: Jignesh Shah, Intel)
Presenter: George Chen (Intel) 11:30 a.m. – 1:00 p.m. Lunch and social networking
1:00pm – 1:45pm Future of Simulation-Based Product Innovation in the Digital World [Keynote] (Chair: Debjit Sinha, IBM)
Speaker: Prith Banerjee (Ansys)

1:45 a.m. – 2:45 a.m. Timing Analysis at Scale (Chair: Peivand Tehrani, Synopsys)

2:45 p.m. – 3:00 p.m. Break

3:00 p.m. – 3:30 p.m. Aging Timing Signoff Solutions for Automotive and IoT Applications (Global Foundries) [Invited] (Chair: Paul Pereira)
Speaker: Siddharth Sawant

3:30 – 4:00 On-premise and AWS Cloud Enablement of Xilinx Design Capture and Closure Flows using Ansys Path FX [Invited] (Chair: Joao Geada)
Speakers: Simon Burke and Nitin Navale

4:00 p.m. – 4:30 p.m. Efficient Parasitic Interconnect Insertion for Timing Analysis [Invited] (Chair: Joao Geada)
Speaker: Prof. Ron A. Rohrer (Southern Methodist University)

4:30 p.m. – 4:45 p.m. Closing remarks & logistics