Important dates
| Paper submission: (Invited paper submission is open) |
Closed |
| Acceptance notification: | Dec 23, 2015 |
| Camera ready paper due (for accepted papers): | Closed |
Call for papers [PDF] [TXT]
It has become clear that timing analysis is NO longer a solved problem. So, what are new challenges as the industry embraces 14/10nm and below, rides the wave of ultra-low-power mobile, wearable devices and jumps on the “Internet of Things” (IoT) bandwagon? How to meet the insatiable demands for accuracy, performance, capacity and functionality? How are multi-core and multi-machine helping? Or is it time to move onto higher levels of abstraction? What about more fundamental challenges coming from process physics, 3D, variability, voltage scaling, analog effects, mixed signal modeling and validation?The TAU series of workshops provide an informal forum for practitioners and researchers working on these and other temporal aspects of analog and digital systems to disseminate early work and engage in a free discussion of ideas. The twenty-third in the TAU series, the TAU 2016 workshop invites submissions and proposals from the traditional as well as emerging areas related to the timing properties of digital electronic systems, including but not limited to the topics listed below.
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Timing (including incremental timing) • System/circuit-level timing • Gate/transistor-level timing • Timing of mixed signal circuits, FPGAs • New types of latches, dual-edge devices, etc. • Distributed timing analysis |
Modeling and simulation • Transistor level modeling • Analog circuit modeling • Circuit level simulation • Delay models and metrics • Aging, reliability modeling and simulation |
| Variability • Timing analysis under uncertainty • Ultra-low voltage induced variation effects • Statistical timing analysis and optimization • Sensitivity/criticality analysis • Yield analysis and optimization |
Power, trade-offs and optimization • Timing issues in low-power design • Power-delay tradeoffs • Layout impact on timing • Timing driven layout optimization • Timing driven synthesis, re-synthesis • Circuit optimization |
| Signal integrity • Crosstalk modeling, analysis, avoidance and optimization • Noise and glitch analysis • Variation-aware signal integrity analysis |
Clocking • Complex clock trees and networks • Clocking, synchronization, and skew • Clock domains, static/dynamic logic • Novel clocking schemes |
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Characterization • Cell (library) characterization • Variation effects and corner reductions • Latch characterization • Simulation and characterization of SRAM circuits |
Hierarchical timing • Timing macro-modeling: timing, SI, power, etc. • Hierarchical optimization and sign-off • Integration/Interoperation with implementation flow |
| Emerging technologies • Full custom design analysis • Smart sensor placement • Timing issues for 3D ICs, TSVs • Timing implications of emerging technologies |
Others • Integrated functional-temporal analysis • Formal theories and methods • Asynchronous systems • Localization and debug of timing errors |
Submission of papers
All papers (including invited papers and camera ready versions) must be submitted electronically using the EasyChair system using the link under the Logistics tab.
Submissions are limited to 8 pages in the double column proceedings format (prefered). TAU is a workshop aimed at fostering a high level of professional interaction, not a conference. Copies of papers will be provided to the attendees, but the proceedings will not be published by the ACM or the IEEE. Therefore, accepted papers can still be submitted to other conferences and journals.
