Technical program
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TAU 2016

ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

March 10-11, 2016
Hilton Sonoma Wine Country, Santa Rosa, California
www.tauworkshop.com

TAU 2016 technical program* [Mar 10] [Mar 11] [PDF]

Thursday, March 10, 2016

8 – 8:45 a.m. Breakfast

8:45 a.m. – 9 a.m. Opening Remarks from general chair
 
9 – 9:45 a.m. Optimizing Automotive Drive Trains: from Energy Source to where the Rubber Meets the Road [Keynote] (Chair: Debjit Sinha, IBM)
Presenter: Patrick Groeneveld (Synopsys)
9:45 – 10:15 a.m. Break

10:15 – 11:05 a.m. Interconnect Modeling and Optimization (Chair: Igor Keller, Cadence) 11:10 a.m. – 12 p.m. Design Reliability (Chair: Oscar Ou, MediaTek) 12 – 2 p.m. Lunch and social networking
 
2 – 2:45 p.m. Timing in Biological Systems [Special session invited talk] (Chair: Vladimir Zolotov, IBM)
Presenter: Louis Scheffer (Howard Hughes Medical Institute, USA)

2:45 – 4:15 p.m. Design Variation and Statistical analysis (Chair: Tom Spyrou, Altera/Intel) 4:15 – 4:30 p.m. Break

4:30 p.m. – 6 p.m. Panel: Can we still have, or even need, timing interoperability in the age of EDA silos?
Organizers: Joao Geada (CLK DA)
Panelists: Florin Dartu (TSMC), Jim Sproch (Synopsys), Paul Penzes (Qualcomm), Ruben Molina (Cadence), Vasant Rao (IBM)

7 p.m. – 9 p.m. Reception

Friday, March 11, 2016

8 a.m. – 8:45 a.m. Breakfast

8:45 a.m. – 9 a.m. Opening Remarks from technical program chair

 
9 – 9:45 a.m. In search of Lost Time [Keynote] (Chair: Qiuyang Wu, Synopsys
Presenter: Andrew B. Kahng (Departments of CSE and ECE, University of California, San Diego)

9:45 – 10:30 a.m. TAU contest: Timing macromodeling (Chair: Qiuyang Wu, Synopsys)
Presenters: Jin Hu (IBM), Song Chen (Synopsys)

10:30 – 10:45 a.m. Break

10:45 a.m. – 12:15 p.m. Advances in Timing Analysis (Chair: Richard Phillips, nVidia)

12:15 – 2 p.m. Lunch and social networking

2 – 3:15 p.m. Timing of FPGAs and Asynchronous Designs (Chair: Hong Li, Xilinx)

3:15 p.m. – 3:30 p.m. Break

3:30 p.m. – 5 p.m. Panel: How low can we go? Challenges when designing at ultra-low voltage
Organizer: Florin Dartu (TSMC)
Panelists: Sriram Vangal (Intel), Christian Lutkemeyer (Broadcom), Satheesh Balasubramanian (ARM), Paul Penzes (Qualcomm), Kelvin Le (Synopsys), Igor Keller (Cadence)

5 p.m. Closing remarks