TAU 2017 timing contest topic:
Timing macro-modeling [Contest
website]
The increase in the size of modern chip designs is forcing a paradigm shift from a traditional "flat timing" model to a "hierarchical timing" model. In the new paradigm, designs may be hierarchically partitioned into sub-blocks (or macros) that are timed in isolation (out-of-context), followed by a generation of a simplified timing macro-model that is plugged at the parent level of hierarchy. This aditionally enables re-use of macros and a parallel chip design and optimization environment.
The TAU 2017 contest will continue extend the coverage on the concept of hierarchical timing via timing macro-models. Modeling efficiency is the emphasied among manyother challenges during timing macro-modeling techniques. The goals of this year's TAU contest are:
- increase awareness of timing analysis and need for timing macro-modeling;
- encourage parallel (multithreaded, distributed) approaches;
- introduce different macro-models and formats, including black-box and gray-box models, encapsulated in industry-standard formats;
- create an evaluation environment to measure the performance of macro-modeling generation and usage in terms of memory, runtime, and accuracy; and
- facilitate a unified academic timing engine in which macro-models are generated and its quality is automatically compared to the original flat-timed design.
The winners of TAU 2017 timing Contests are
- First Place : iTimerM 2.0
Pei-Yu Lee, Iris Hui-Ru Jiang
National Chiao Tung University, Taiwan - Second Place: LibAbs
Tin-Yin Lai, Martin D. F. Wong
University of Illinois at Urbana-Champaign, IL, USA
Prior year contests
- 2016: Timing Macro-Modeling
- 2015: Incremental timing and CPPR
- 2014: Common path pessimism removal (CPPR)
- 2013: Variation aware timing
- 2012: Power grid simulation
- 2011: Power grid simulation
