The ACM sponsored TAU series of workshops provide an informal forum for practitioners and researchers working on temporal aspects of digital systems to disseminate early work and engage in a free discussion of ideas. The twenty-fourth in the TAU series, the TAU 2017 workshop emphasizes novel aspects of timing and power analysis as well as optimization with special invited talks.
News/Announcements
* TAU'17 was successfully held at Monterey Marriot on 3/16-17, 2017. Registered attendees come from Academia, EDA, design houses, foundries, including UIUC, UC Berkley, Univ. of Utah, Kyoto Univ. (Japen), NCT Univ. (Taiwan), AMD, Analog Devices, ARM, Broadcom, IBM, Intel, Inphi, MediaTek, Qualcomm, Renesas, Samsung, TI, TSMC, Xilinx, Synopsys, Cadence, Ansys, CLKDA, Arcadia. (see pictures)
Special sessions, keynotes and invited talks in TAU 2017
(in program order) |
Title: Recent Advances in Timing Analysis by: Prof. Martin D. F. Wong Executive Associate Dean, College of Engineering Edward C. Jordan Professor of ECE University of Illinois at Urbana-Champaign, USA |
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Title: Are You Ready to Re-time Your Design? by: Dr. Mahesh A. Iyer Intel Fellow, Chief EDA Architect Intel Corporation, USA |
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Title: Challenges in Power Integrity Analysis by: Bill Mullen Senior Director of Research & Development, Semiconductor Business Unit Ansys Inc. USA |
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Title: Rogue Waves, On-Chip Power Integrity and Static Timing Analysis by: Dr. Christian Lutkemeyer Senior Technical Director, ASIC Inphi, USA |
TAU 2017 is organizing a timing contest. The topic for the TAU 2017 contest is an extension to Timing macro-modeling, similar to last year, but with added emphasis on the efficiency of both model generation and model consumption. Winners of the contest will be awarded plaques as well as cash prizes!
Conference organizers
- General chair: Qiuyang Wu (Synopsys)
- Technical program chair: Tom Spyrou (Intel)
- Past general chair: Debjit Sinha (IBM)
- Contest chair: Song Chen (Synopsys)
