Technical program
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TAU 2017

ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

March 16-17, 2017
Monterey, California
www.tauworkshop.com

TAU 2017 Technical Program

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[Mar 16, 2017] [Mar 17, 2017] [PDF]


Program Details *

Thursday, March 16, 2017

8 – 9:00 a.m. Breakfast

9 a.m. – 9:15 a.m. Opening Remarks from general chair
 
9:15 – 10 a.m. Recent Advances in Timing Analysis[Keynote] (Chair: Qiuyang Wu, Synopsys)
Presenter: Prof. Martin Wong (ECE, University of Illinois Urbana-Champaign)
10 – 10:15 a.m. Break

10:15 – 11:15 a.m. Interconnect and Cell Modeling (Chair: Subra Sripada, Synopsys) 11:15 a.m. – 12 p.m. Adventures in Candy Land [Invited](Chair: Qiuyang Wu, Synopsys)
Presenter: Bogdan Tutuianu (TSMC)
Authors: Rahul Krishnan, Bogdan Tutuianu, Florin Dartu (TSMC)


12 – 2 p.m. Lunch and social networking
2 – 2:45 p.m. Are You Ready to Re-Time Your Design? [invited] (Chair: Joao Geada, CLK-DA)
Presenter: Mahesh Iyer (Intel)
2:45 a.m. – 4:05 p.m. Design Optimization (Chair: Tom Spyrou, Intel)
4:05 – 4:30 p.m. Break

4:30 p.m. – 6 p.m. Panel: Aging Effects Modeling and Analysis
Organizers: Christian Lutkemeyer (inPhi)
Panelists: Debjit Sinha (IBM), Andrew Kahng (UCSD), Igor Keller (Cadence), Mehmet Avci (Intel), Paul Penzes (Qualcomm), Patrick Groeneveld.

7 p.m. – 9 p.m. Reception



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Friday, March 17, 2017


8 a.m. – 9 a.m. Breakfast

9 a.m. – 9:15 a.m. Opening Remarks from technical program chair

9:15 – 10:45 a.m. Special Invited Sessions on Rail, Power and Timing(Chair: Jindrich Zejdaj, Xilinx)

9:15 – 10 a.m. Challenges in Power Integrity Analysis
Presenter: Bill Mullen (AnSys)

10 – 10:45 a.m. Rogue Waves, On-Chip Power Integrity, and Static Timing Analysis
Presenter: Christian Lutkemeyer (inPhi)

10:45 – 11 a.m. Break


11 – 11:45 a.m. TAU contest: Timing Macro Modeling (Chair: Tom Spyrou, Intel)
Presenters: Song Chen (Synopsys)

11:45 – 12:15 p.m. A New SSTA Method Based On Birnbaum-Saunders Distribution (Chair: Song Chen, Synopsys)
Presenters: Mikhail Chetin, Praveen Ghanta(Cadence)
Authors: Mikhail Chetin, Praveen Ghanta, Igor Keller(Cadence)

12:15 – 2 p.m. Lunch and social networking

2 – 3 p.m. Design Reliability (Chair: Oscar Ou, MediaTek)

3 – 4:30 p.m. Panel: Challenges and Advances in Rail Analysis and Voltage Variation Aware STA
Organizer: Igor Keller (Cadence)
Panelists: Christian Lutkemeyer (inPhi), Jim Dodrill (ARM), Paul Penzes (Qualcomm), Haish Kriplani (Synopsys), Suketu Desal (Cadence), Bill Mullen (Ansys).

4:30 – 5 p.m. Closing remarks & logistics