The ACM sponsored TAU series of workshops provide an informal forum for practitioners and researchers working on temporal aspects of digital systems to disseminate early work and engage in a free discussion of ideas. The twenty-sixth in the TAU series, the TAU 2019 workshop emphasizes novel aspects of timing and power analysis as well as optimization with special invited talks.
News/Announcements
Registration is open! Register on the logistics page here. Book your hotel before 3/8, you can pay at discounted rate and stay at conference hotel where all the activities happen.
Special sessions, keynotes and invited talks in TAU 2019
* TAU'19 will be held at Monterey on 3/21-22, 2019. Registered attendees come from Academia, EDA, design houses, foundries, including Democritus University of Thrace, Duke University, National Chiao Tung University, UC Berkeley, UC SD, UT Austin, Yale, Synopsys, Cadence, Ansys, Arcadia, Parallax, ARM, Broadcom, IBM, Inphy, Intel, MediaTek, nVidia, Qualcomm, ST. (see pictures from recent workshop)
Special sessions, keynotes and invited talks in TAU 2019
(in program order) |
Title: Beyond CMOS – A Look at Two Promising Post CMOS Technologies: Superconducting Electronics & Spintronic (abstract) by: Jamil Kawa Synopsys Fellow |
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Title: Time as a First-Class Object in Systems (abstract) by: Rick McGeer Co-founder and CEO engageLively |
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Title: Where is my “Typical” Chip? Relating Silicon Back to the Timing Sign-Off Model (abstract) by: Christian Lutkemeyer Senior Technical Director Inphi |
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Title: From Recovering Time to Timing Recovery: Some Challenges for the TAU Community (abstract) by: Andrew B. Kahng Professor University of California, San Diego |
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Title: Deep Neural Networks’ Applications in EDA and Their Acceleration Techniques (abstract) by: Yiran Chen Associate Professor Duke University |
Timing Contest
TAU 2019 is organizing a timing contest. The TAU 2019 contest will focus on the performance of an optimization tool, in terms of final timing, area, and power. The specific objective is to develop a runtime and memory efficient approach to speed up closure flow. Winners of the contest will be awarded plaques as well as cash prizes!
Conference organizers
- General chair: Song Chen (Synopsys)
- Technical program chair: João Geada (Ansys)
- Past general chair: Tom Spyrou (Intel)
- Contest chair: George Chen (Intel)
